Jorge Posted December 11, 2016 Report Share Posted December 11, 2016 Hi there, I'm an engineering student from Venezuela and working on systemC for a class project. I'm having a bad time trying to make a tri-state buffer model on system C. I know there is sc_logic and sc_lv but I just don't know how to work with this two data types. I'm working a project (a microprocessor) and I need to model a tri-state module to hook up with my registers so I'll be able to have control on the data coming out of the registers. In case you wonder here is more info https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Build/implRegFile.html Any idea on how to model a tri-state buffer module?. thanks in advance. Quote Link to comment Share on other sites More sharing options...
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