Best practice to specify global memory map for top level design config

[tjroamer]

In our design, there are one processor, one bus and several peripherals. Is it possible to create a memory map from the master port to all of the slave ports of the peripherals? For different designs, the memory map should be different. Finally I want to generate information from IP-XACT files like the following:

DesignCfg1:
ARM.IAHB:
    Peri1.AHB: 0x2000_0000 - 0x2000_FFFF
    ....
    Perix.AHB: 0x3000_0000 - 0x3000_0FFF
ARM.DAHB:
    Peri1.AHB: 0x4000_0000 - 0x4000_FFFF
    ....
    Perix.AHB: 0x4001_0000 - 0x4001_0FFF

DesignCfg2:
ARM.IAHB:
    Peri1.AHB: 0x1000_0000 - 0x1000_FFFF
    ....
    Perix.AHB: 0x2000_0000 - 0x2000_0FFF
ARM.DAHB:
    Peri1.AHB: 0x3000_0000 - 0x3000_FFFF
    ....
    Perix.AHB: 0x3001_0000 - 0x3001_0FFF

I cannot do that in the processor local address space, because the processor has to be instantiated many times with different address mappings to the master ports. In fact, this information belongs to design.

[tjroamer]

Is this a design flaw in the IP-XACT standard? I think address spaces should have belonged to "Design" top level element instead of "Component". What is the rational behind this design decision? 

[kock]

Hello,

Sorry for replying this late. The rational is that the global memory map is computed from the design connectivity. The components should be reusable. For instance, if you swap bus components with different addressing, then the cpu component should not be affected. Hence, the global memory map is not described in the cpu component. De cpu component only describe its addressable space and not what is all mapped into this space.

Furthermore, the global memory map is independent of IP-XACT design configurations (unless the design configurations configure different hierarchical views). The design connectivity is described in IP-XACT designs. What you can describe, is that you have multiple hierarchical views in a component. These hierarchical views can reference different designs. However, the IP-XACT semantic consistency rules (SCR 11.3) state that the global memory maps for each bus interface in an hierarchy of bus interfaces must be equal. So you can describe the scenario mentioned in your email as long as the bus interfaces of the top component adhere to this rule.

Best regards,
Erwin