tjroamer Posted August 5, 2016 Report Share Posted August 5, 2016 In our design, there are one processor, one bus and several peripherals. Is it possible to create a memory map from the master port to all of the slave ports of the peripherals? For different designs, the memory map should be different. Finally I want to generate information from IP-XACT files like the following: DesignCfg1: ARM.IAHB: Peri1.AHB: 0x2000_0000 - 0x2000_FFFF .... Perix.AHB: 0x3000_0000 - 0x3000_0FFF ARM.DAHB: Peri1.AHB: 0x4000_0000 - 0x4000_FFFF .... Perix.AHB: 0x4001_0000 - 0x4001_0FFF DesignCfg2: ARM.IAHB: Peri1.AHB: 0x1000_0000 - 0x1000_FFFF .... Perix.AHB: 0x2000_0000 - 0x2000_0FFF ARM.DAHB: Peri1.AHB: 0x3000_0000 - 0x3000_FFFF .... Perix.AHB: 0x3001_0000 - 0x3001_0FFF I cannot do that in the processor local address space, because the processor has to be instantiated many times with different address mappings to the master ports. In fact, this information belongs to design. Quote Link to comment Share on other sites More sharing options...
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