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tjroamer

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  1. Is this a design flaw in the IP-XACT standard? I think address spaces should have belonged to "Design" top level element instead of "Component". What is the rational behind this design decision?
  2. In our design, there are one processor, one bus and several peripherals. Is it possible to create a memory map from the master port to all of the slave ports of the peripherals? For different designs, the memory map should be different. Finally I want to generate information from IP-XACT files like the following: DesignCfg1: ARM.IAHB: Peri1.AHB: 0x2000_0000 - 0x2000_FFFF .... Perix.AHB: 0x3000_0000 - 0x3000_0FFF ARM.DAHB: Peri1.AHB: 0x4000_0000 - 0x4000_FFFF .... Perix.AHB: 0x4001_0000 - 0x4001_0FFF DesignCfg2: ARM.IAHB: Peri1.AHB: 0x1000_0000 - 0x1000_FFFF .
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