marco711 Posted July 2, 2016 Report Share Posted July 2, 2016 Hello, I'm writing a module in SystemC which basically works as follows: it receives a string of bytes through a port p_in and a control signal through the port h. The module must save the bytes within a matrix matrix just if the h signal is true. Within the SC_THREAD I'm using I implemented this: void MY_MODULE::my_method(){ if(!rst){ //put all the output ports to 0 } while(1){ //The module waits while the signal h is false while(!h) wait(); //The iterations to fill in the matrix begin //The iterations must work just if h = true for(i=0; i<100; i++){ for(j=0; j<100; j++){ matrix.nmmatrix[i*matrix.width+j] = p_in; wait(); while(!h) wait(); } } } } The problem I have is that the counters i and j start to increment one clock cycle after h passes from false to true. The behavior I'm trying to simulate is that the counters i and j start to increment in the same clock cycle when h passes from false to true and the counters must not increment while h is false. Could you please give a hint of what I am doing wrong? Quote Link to comment Share on other sites More sharing options...
apfitch Posted July 4, 2016 Report Share Posted July 4, 2016 It looks to me that if you assign h true and the first value to p_in using the same clock as your process, then it should work, i.e. you should be able to sample p_in with i = 0 and j = 0 correctly. It's hard to say without seeing now you are applying the stimulus to h and p_in. regards Alan Quote Link to comment Share on other sites More sharing options...
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