Connecting modules

[MikeStrom]

Hi,

 

I'm learning SystemC and have a question.

 

I have a bus of signals origin from one module that needs to be split up and routed to several other modules.

 

For example 

SC_MODULE(A) {
  sc_out< sc_bv<14> > gpio_bus_out;
  sc_in< sc_bv<14> gpio_bus_in;
  ...
};

needs to be split to a number of modules, i.e the following module are to receive bits 1:0;

SC_MODULE( { 
  sc_in< sc_bv<2> > bits_1_0_in;
  sc_out< sc_bv<2> > bits_1_0_out;
  ...
};

Is there a way to do this directly by wiring, or do i need to create a module to connect them?

 

Thanks in advance,

Mike

 

[apfitch]

In SystemC 2.2 the only option was to add a module or a process (SC_THREAD/SC_METHOD) to do the work. Since 2.3, there's the sc_vector class which is intended for just this kind of job. It's described in the Language Reference Manual which you can download free via the link on accellera.org,

 

Alan

[MikeStrom]

In SystemC 2.2 the only option was to add a module or a process (SC_THREAD/SC_METHOD) to do the work. Since 2.3, there's the sc_vector class which is intended for just this kind of job. It's described in the Language Reference Manual which you can download free via the link on accellera.org,

 

Alan

 

Thanks Alan,

 

I can't find the LRM for 2.3. Where is it?

 

in my case, module A in the example above is generated by verilator, so i can't change the type. I could however change module B to what ever would aid the situation.

[apfitch]

Go to http://www.accellera.org/downloads/standards/systemcthen at the bottom of the page click "Find out more and how you can download it".

 

sc_vector lets you assemble and disassemble ports and signals into and from busses - so I think you could use it in the enclosing module (the module that instances module A and module . Or just add a couple of SC_METHODs, one to split the inputs to module B, and one to put together the ouputs of module B.

 

regards

Alan

[MikeStrom]

Thanks Alan, i finally found it :-)

 

Many thanks for the help, most appreciated!

 

On another subject; is there a way to remove the requirement for binding output ports in SystemC? 

 

I realize input ports must be bound, but I find it increasingly annoying that unused output ports from our verilator modules (usually declared as sc_out) must be bound. We use SystemC as a verification tool for a huge base of verilog code and all ports are not required or applicable for simulation.

 

Regards,

Mike

[apfitch]

There's no automatic way. You can alter the "port binding policy" of the port, but that would require editing the automatically generated code.

What you can do is create "dummy" signals and bind them to unused ports in the before_end_of_elaboration() callback.

 

You could do that using a post-processing script.

 

Or I guess with some clever code running in the before_end_of_elaboration() callback, as the SystemC library does give you the ability to scan through modules for objects of type sc_out, and then you could use port.size() to find out how many channels were bound. If no channels are bound, create a dummy channel and bind it. You'd have to create the dummy channel of the correct type, which might require some bodgy code to work out the type.

 

The script approach sounds easier :-)

 

Alan