Jump to content


  • Content Count

  • Joined

  • Last visited

Everything posted by MikeStrom

  1. Thanks Alan, i finally found it :-) Many thanks for the help, most appreciated! On another subject; is there a way to remove the requirement for binding output ports in SystemC? I realize input ports must be bound, but I find it increasingly annoying that unused output ports from our verilator modules (usually declared as sc_out) must be bound. We use SystemC as a verification tool for a huge base of verilog code and all ports are not required or applicable for simulation. Regards, Mike
  2. Hi Hans, thanks a lot for the patch. Will try it out! Cheers, Mike
  3. Thanks Hans, I noticed that no hierarchy is created by SystemC in the vcd files. However, i found this utility that adds proper hierarchy to the vcd. It works, except that some incompatibility prevents optimization of the vcd by gtkwave. Am i having this problem because I'm doing something wrong? Chers, Mike
  4. Thanks Alan, I can't find the LRM for 2.3. Where is it? in my case, module A in the example above is generated by verilator, so i can't change the type. I could however change module B to what ever would aid the situation.
  5. Hi, I'm learning SystemC and have a question. I have a bus of signals origin from one module that needs to be split up and routed to several other modules. For example SC_MODULE(A) { sc_out< sc_bv<14> > gpio_bus_out; sc_in< sc_bv<14> gpio_bus_in; ... }; needs to be split to a number of modules, i.e the following module are to receive bits 1:0; SC_MODULE( { sc_in< sc_bv<2> > bits_1_0_in; sc_out< sc_bv<2> > bits_1_0_out; ... }; Is there a way to do this directly by wiring, or do i need to create a module to connect them? Thanks in advance, Mike
  6. Hi, I'm new to SystemC, but have worked with Verilator/C++ for quite a while. We are now moving to Verilator/SystemC and have problems creating hierarchical vcd dumps from SystemC native vcd generation. The only hint i got from the documentation is to use dots to separate hierarchical levels, but it does not create a hierarchy in the vcd files. I attached two screen dumps from gtkwave. The first one is a vcd generated from Verilator, the second is a vcd generated from SystemC. Any suggestions are most welcome. Regards, Mike
  • Create New...