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UVM RAL and uvm_reg_data_t: how is X handled?

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I have had the worst nightmare with VMM handling Xs because the VMM hides Xs by declaring the register data as bit and not as logic. This makes it a royal pain to debug Xs, and the only way out is to assume that all Xs are bad by putting the following code in the xactor:

if ($isunknown(tr.data))
  `vmm_fatal(log,"Register has X: addr=%h data=%h",tr.addr,tr.data);
Is UVM like this or not?
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the uvmreg register model uses "bit" to store values. i think that is correct because as an abstract model it only deals with zeros+ones. in case you want to detect 'X,'Z you can do so by looking at the return code of the operation and check via UVM_HAS_X if the conversion of the bus operation to the register value involved 'X. if you want that check in general simply add it to your bus2reg adapter conversion function.


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I need all the info (thread originating the transaction, register name and logic value) in one place (the bus driver) or another (the caller). Does UVM give me this?

Since the bus driver drives the physical wires, it knows exactly about the Xs and Zs. But does it know the register name and which thread made the call? Can it be told this info so an error report complete with register name and caller info (thread, file and line) can be printed (assuming my vendor did a decent job with %m or some form of stack trace string)?


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