[uvm_reg] best effort front door access does not work?

[SeanChou]

Hi, exports,

uvm1.1 class reference illustrate the "best effort" access in uvm_reg filed write (front door).

If a front-door access is used, and if the field is the only field in a byte lane and if the

physical interface corresponding to the address map used to access the field support

byte-enabling, then only the field is written.

however, my test does not work. a 32-bit reg reg32 contains 4 fields byte0, byte1, byte2, byte3.

my code:

reg32_inst.byte0_inst.write(status, 0x88);

then the adaptor still recevie the below uvm_reg_bus_op

d= 0x0000_0088

nbits = 32

byte_enable = 0x1111 (expected to be 0x0001)

Any hint for debuging this? thank you very much!

[SeanChou]

After update to uvm 1.1a, This problem still persists in my case. perhaps some mistakes of mine, could anyone give me a hint? thanks!

regmodel.reg1_f1.set(5);

regmodel.reg1_f2.set(6);

regmodel.reg1_f3.set(7);

regmodel.reg1_f4.set(8);

regmodel.reg1.update(st); -> write 4 bytes

regmodel.reg1_f1.set(3);

regmodel.reg1_f2.set(4);

regmodel.reg1.update(st); -> still write 4 bytes // but half word access is expected.

[janick]

Tjis is the expected behavior. uvm_reg::update() will update the entire register. Sub-register access is only supported when accessing fields (which are alone in their byte lane and the protocol for the address map supports byte enables).

[SeanChou]

Thanks Janick's response.

however, if update() writes the entire word. which function could perform the best effort front door access?

I tried filed.write as below, but the byte_en and n_bits of the uvm_reg_bus_op is still "ff" and 0x20.

regmodel.reg1_f1.write(st, 1);

thnaks!

[amitshere]

You need to set the "supports_byte_enable" in extensions of uvm_reg_adapter if the bus protocol supports byte enables.

[SeanChou]

Thanks Amit!

with your suggestion to set supports_byte_enable =1, the following line could perform byte access.

regmodel.reg1_f1.write(st, 1); // nbits = 8, byte_en = 1

regmodel.reg1_f2.write(st, 1); // nbits = 8, byte_en = 2

regmodel.reg1_f3.write(st, 1); // nbits = 8, byte_en = 4

regmodel.reg1_f4.write(st, 1); // nbits = 8, byte_en = 8

Another question, any seggustion on how to perform the halfword access? thanks!

[amitshere]

Sean, If a field occupies 2 byte lanes, you can perform a halfword access through a fld.write()..

Otherwise, you will have to do a register.write()/update() but manually override the byte_enable property in the adapter.. for the adapter to understand when to override, it can query the extension argument.. see

http://www.uvmworld.org/forums/showthread.php?489-uvm_reg-read()-and-write()-documentation