How should I design multiple writers?

[rtmc]

I am trying to design a simple system in SystemC. Its just for educational purposes.

 

Basically, I have a module Random, that generates random numbers, and a module Square, that takes a number and give back its square.

 

Its ok when I have only 1 object of each module active. But how sould I do it if I have 2 instances of Random trying to use 1 instance of Square?

 

I was trying to write in Square just 1 port in and 1 port out. But it is not allowed to have a FIFO with multiple writers. Im quite confused on how I should implement this. My current idea (which I feel is not right) is to write my own channel (that will have multiple primitive channels inside) and will work to join all data received from this primitives.

 

Thanks

[dakupoto]

I am trying to design a simple system in SystemC. Its just for educational purposes.

 

Basically, I have a module Random, that generates random numbers, and a module Square, that takes a number and give back its square.

 

Its ok when I have only 1 object of each module active. But how sould I do it if I have 2 instances of Random trying to use 1 instance of Square?

 

I was trying to write in Square just 1 port in and 1 port out. But it is not allowed to have a FIFO with multiple writers. Im quite confused on how I should implement this. My current idea (which I feel is not right) is to write my own channel (that will have multiple primitive channels inside) and will work to join all data received from this primitives.

 

Thanks

Hello Sir,

As you have found out yourself, multiple writer feature is not supported

by the built-in channel classes. Have you looked into the possibility of

creating your own channel ? Alternatively, have you considered the

option of a shared memory with multiple readers and writers, coupled

with blocking reads/writes -- please check the built-in concurrency control

classes as sc_mutex, sc_semaphore. Hope that helps.

[ralph.goergen]

Hi,

 

SystemC tries to preserve you from implementing undefined behaviour as much as possible. There is an option to allow multiple writers but, in general, this is not what you want.

If two processes write to a signal or fifo in the same delta cycle, the order of write accesses is not deterministic.

In your case, there are several options:

Writing your own channel, e.g. a bus model.

Writing some kind of de-multiplexer.

...

 

In all cases, you have to think about what happens if more than one process tries to access the component conrurrently. And you have to define some kind of order between the input ports or a communication protocol.

 

Greetings

Ralph

[rtmc]

Thanks, I'm going to think a bit on shared memory, but probably going to start trying my own channel with a bus model. It was very helpful.