macro expansion error with minimalistic import

[loki]

The error:

Following verilog source has syntax error :
  "myBfm.sv", 12 
  (expanding macro): token is '#'
    `uvm_component_utils(myBfm)

The code:

`include "uvm_pkg.sv"
import uvm_pkg::uvm_component;
class myBfm extends uvm_component;
  `uvm_component_utils(myBfm)
...

First I did not understand, because this looked exactly like the in examples.

Then I decided that instead of importing only the symbols each file needed (e.g. import uvm_pkg::uvm_component), I would try to import everything at the top level (i.e. import uvm_pkg::*). Doing so, the error went away, but the compiler simply hangs forever during parsing with not hints as to what is wrong.

[adielkhan]

The error seemed to indicate the macro was the issue.

Perhaps you were not doing `include "uvm_macro.svh"

The simulator parsing not returning seems like a bug you should file with the simulation vendors.

-adiel.

[loki]

The uvm_pkg.sv file already includes the macros... this leads me to believe both problems have to do with the compiler.