kuncikehidupan Posted July 6, 2015 Report Share Posted July 6, 2015 Hi all, After developing a virtual platform using SystemC with TLM, and also several peripherals (IP) model in high-level (LT), I realised that if in RTL design there is a UVM to say that the design is "okay". How about in high-level? Is there any methodology that we could adopt?If there is none, may I ask for your suggestion on how to verify our own SystemC TLM (LT) design? The SystemC Verification subforum seems to be obsolete, so I posted it here. Really appreciate any kind of advice and solution. Thank you. Regards, Arya. Quote Link to comment Share on other sites More sharing options...
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