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UVM-ML Open Architecture
Version version 1.12
4,179 downloadsUVM-ML Open Architecture - version 1.12 Enabling Multi-Language and Multi-Framework Verification May, 2022 General Overview Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies. This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license. This distribution includes the following main elements Backplane implementation and API Example frameworks and adapters (three provided: UVM-SV, UVM-e, and UVM-SC) Several demos and high level examples (showing all frameworks interacting) and a few smaller feature examples (tests) Docs directory with a Reference manual, User Guide and reference HTML docs Information on all news and features can be found in the ml/docs/ directory. This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. Please read the “Status, Use, and Disclaimers” section below for full details. Where to Find Information Where to start reading: point your web browser to ml/README.html The landing page provides links to installation directions, release notes, user guide, and more. For feedback or questions: send email to email@example.com An easy installation and Setup video guide is available You can checkout the update of David I. Long form Doulos at DVCon 2016 in the US. It relates to UVM-ML (along with other updates). Blog series: Multi-Language Verification Environment—Getting First Run in Few Minutes Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using UVM ML Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi-Language Environment Multi-Language Verification Environment (#4)—Multi-Language Hierarchy Debugging Multi-Language Verification Environments UVM-ML- Managers’ Freedom of Choice Platforms and Simulators This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages. ------------------------------------------------------------------------------------------------------- UVM-ML Open Architecture: Status, Use, and Disclaimers This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution. The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact firstname.lastname@example.org Use and Disclaimers: Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom). Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected. Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes. Quality: this package is still under development. It is being tested and regressed with all active versions of Incisive and with the Accellera OSCI simulator before being released. The user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed. Standardization: This package is not a standard. However, it is available as open source to all potential users. Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed. Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs. ------------------------------------------------------------------------------------------------------- What's new in each version For the full listing and more details please see the release-notes.txt file at the top of the release package. Please note that the items in red might require some changes on the user's side while upgrading to this version, please read these items carefully in the release notes. 1.12 The support for UVM-SV IEEE (2017) (with ML customizations) is now available. 1.11.1 Compatible with Xcelium 2021.03 (with CXX11 ABI) g++ 9.3 and CXX11 ABI (-D_GLIBCXX_USE_CXX11_ABI=1) are now supported. install*.csh now accept --use-cxx11-abi / --no-use-cxx11-abi. This sets UVM_ML_ABI_CXXFLAGS behind the curtains, respectively to -D_GLIBCXX_USE_CXX11_ABI=1 and -D_GLIBCXX_USE_CXX11_ABI=0. UVM-ML no longer interferes with uvm_objection::set_propagate_mode. When using with Xcelium, a proper warning should now be issued if both the command line "-uvmtop/-uvmtest" and uvm_ml_run_test parameters are provided. UVM-SC adapter code was reworked to avoid unnecessary thread spawning, thus improving performance and avoiding crashes in some cases 1.11 Support for calling uvm_ml_run_test() from SV program block (instead of a SV module) is now added. Note that this means that UVM Runtime phases are now blocking by default on procedural runs. Please refer to the documentation of uvm_ml_run_test() for more details. For OSCI users: "sc_simcontext::co_simulate" ML enabler is dropped, sc_start is used instead. This helps ensuring that the SystemC callbacks are separated for static vs quasi-static entities Enhanced error handling Enhanced examples- the options to run examples for multi steps with xrun and also bitness are now supported (see demo.sh -help ). 1.10.2 Supporting TCL 8.6 as of Xcelium 18.11 1.10.1 Fully qualified with IES version 15.2 and Xcelium 17.10-18.09 (the earlier version:1.10 has an issue with 18.09, which is fixed in this version). Questa 10.6b is supported 1.10: Fully qualified with IES version 15.2 and Xcelium 17.04-18.03. ASI (OSCI) 2.3.2 is supported. Support for OSCI 2.2 was dropped. Open source version can be accessed by pre-processor macros (SystemC only: UVM_ML_CURRENT_NUMERIC_VERSION and UVM_ML_NUMERIC_VERSION) or by a method (get_numeric_version) Enhancements and fixes in event propagation between frameworks Improved error handling Other fixes 1.9: Fully qualified with IES version 15.2 and Xcelium 17.04-17.10. In order to make it work with Xcelium 18.03, you can just comment the patch header in ml/adapters/uvm_e/sn_uvm_ml.e. Runtime phase synchronization between UVM-e to UVM-SV is now supported in UVM-ML OA (only with Xcelium 17.10). System C TLM2 convenience sockets (including passthrough_initiator/target_socket) are now supported by UVM-ML OA. 1.8 Fully qualified with IES version 15.2 and Xcelium 16.11-17.04. New debug command for tracing serialization in SV and e : uvm_ml trace_ser Moving from one Xcelium agile version to the other requires reinstallation of UVM-ML (running install_xclm.csh again) against the respective version) and no additional manual steps are needed 1.7: Fully qualified with IES version 15.2 and Xcelium 16.11-17.02. New debug command for observing matching types was added: "uvm_ml print_type_match". Support for multiple ML connections for SystemC TLM2 sockets. 1.6: Fully qualified with IES versions 14.2,15.1 and 15.2. UVM-SV 1.2 is now fully supported (please read RELEASE_NOTES.txt under ml directory for more details). When working with Incisive 15.2, the user can take some steps in order to skip compiling the e part of the adapter (this might be important for users that compile other e code on top of Specman, like VIP). The steps are documented in the UVM-ML OA user guide under: "Linking the Specman UVM-e Adapter From Incisive Version 15.2 On". OSCI 2.3.1 is now supported instead of OSCI 2.3, meaning that the supported OSCI versions are: 2.3.1 and 2.2. gcc 4.8.3 is now supported 1.5.1: Fully qualified with IES versions 14.1,14.2 and 15.1. Early adopters UVM-SV 1.2 support for IES (please read RELEASE_NOTES.txt under ml directory for more details). UVM-ML tcl commands are now available from Specman with all supported simulators. UVM-ML tcl commands are renamed (they all start with uvm_ml prefix, followed by a space and the command name, e.g uvm_ml print_tree). The old names are still supported. Pre-compiled UVM-SC parts for IES were eliminated. Examples are enhanced and extended. Updated the Backplane API version number. New debug commands in IES to print the UVM-ML tree, port connections, and port registrations. Brand-new documentation including User Guide, Reference Manual and more. Support for IES reset in UVM-ML environment. Support for sharing uvm_events and uvm_barriers between UVM-SV and UVM-SC. Support for +UVM_TESTNAME in all simulators and languages. Passing tlm_generic_payload transactions via analysis ports. Several ASI SystemC enhancements: Automated synchronization, ML-registering of SC TLM2 sockets. Reorganized examples to make them more useful. Enhanced and simplified installation and setup. 1.5: Fully qualified with IES versions 13.2, 14.1, and 14.2. "Phase Debug" feature, for setting breakpoints at the beginning or end of UVM-ML phases (see the Integrator User Guide for details). Currently this works only for IES. Added support for the generic UVM SV syntax, uvm_config_db#(T), so that it now works also for ML configuration Improved the way to run the demo examples and to learn how to run UVM-ML Reduced the amount of ML enabling modifications introduced into the local version of UVM-SV (1.1d), by enhancing the UVM-SV adapter implementation 1.4.4: The e macro uvm_ml_stub_unit now directly sets unit attributes hdl_path() and agent(), thus saving the user a need to add auxiliary string fields Improved the handling of UVM-ML bitness (once users select 32 or 64 bit mode, the library and all examples will run in that mode) Enhanced sequence layering capabilities Enhanced the test_env.csh script to provide more validity testing of the user's environment and to provide better suggestions how to fix issues irun_uvm_ml.*.f option files were reorganized (including a name change): IES irun invocation options were grouped into several option files, reflecting the usage context, and adding comments to clarify their meaning This release might require some changes on the user's code while upgrading to this version, see details in the release_notes.txt” 1.4.2: Fully qualified with IES version 14.1 Enables usage of Cadence UVM extensions on top of UVM-ML OA Support for UVM ML configuration tracing on the SV side, activated by the +UVM_CONFIG_DB_TRACE command-line option Added new backplane API functions enabling the time notification (wakeup) service and updated the backplane API version number Updated the sequence layering examples. The code is simplified and type conversion using mltypemap is demonstrated Eliminated the UVM SV warnings Mechanism to recognize whether OSCI was compiled with pthreads and compile the custom sc_simcontext.cpp accordingly 1.4.1: New examples showing basic TLM communication Default installation is 32bit instead of 64bit Setup and install scripts renamed UVM-SC has been updated with a standalone phase controller that can run through the common and UVM phases. In addition user defined schedules, which can be synchronized with the standard UVM phases, are supported as well. Enhanced UVM-SC to support run_test() in the SC-standalone mode (not collaborating with other frameworks) Methodology and examples for sequence layering across languages Enhancements in how unified hierarchy works 1.4: Support for uvm-1.1d (in place of uvm-1.1c) Addition of a portable UVM-SC adapter. Simulator independent and tested to run on several simulators Architected to be highly modular and extensible A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies) Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC Enables creating a unified hierarchy of components of different frameworks 1.2.2: Multi-Language configuration Support of TLM1 and TLM2 communication between all the provided frameworks Enhanced synchronization of test phases and delegation of phasing control to a designated framework
To All Design and DV Engineers! Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. There are some limitations on side of assertion cover properties but rest it compile complete SV and UVM including constraints and randomization. Learning UVM without hands-on is difficult. I believe this is opportunity for students, engineers and hobbyists to skill up without relying on paid or online tools as now you can run UVM on your system. For getting started, even though there are many UVM generators, I believe the starters need simple easy to use UVM generator tool. I found the ones available online like Easier UVM or UVMF quite difficult to use and even interact with. I developed a open-source tool "tbengy" to generate a UVM TB and Makefile that will readily get you started and will run on Vivado Simulator. You can read the instructions on https://github.com/prasadp4009/tbengy Hope it helps you all!
Hello All, Please tell me the difference between transaction class and uvm_sequence_item class? Please provide me the clarity on the get_sequence_id method in uvm_sequence_item class Please provide me the clarity on the accept_tr , end_tr, start_tr in uvm_transaction class
Hi all, After developing a virtual platform using SystemC with TLM, and also several peripherals (IP) model in high-level (LT), I realised that if in RTL design there is a UVM to say that the design is "okay". How about in high-level? Is there any methodology that we could adopt? If there is none, may I ask for your suggestion on how to verify our own SystemC TLM (LT) design? The SystemC Verification subforum seems to be obsolete, so I posted it here. Really appreciate any kind of advice and solution. Thank you. Regards, Arya.
UVM 1.2 feedback required
adielkhan posted a topic in UVM Commercial AnnouncementsDear all, As we close in on delivering UVM 1.2 to the engineering community now is the time for you to read the docs, review the code, test the functionality. Or as they say forever hold your peace..... Once approved changing documentation requires another full review so really please do give your feedback ASAP. As a UVM user it is in your interest that UVM meets your requirements and your opinion is considered. There is a list of issues we know about within the Mantis database: http://www.eda.org/svdb/my_view_page.php If you want to view the code for a particular branch from sourceforge you can do so from your browser. http://sourceforge.net/p/uvm/code/ref/master/branches/ On the left click ""More Branches" UVM 1.2 will be built from the UVM_1_2 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2/tree/ At the time of writing the latest HTML docs are generated from RC4 branch: http://sourceforge.net/p/uvm/code/ci/UVM_1_2_RELEASE_RC4_WITHHTMLDOC/tree/ It is just as easy to grab the latest code for you to run with your own projects for testing. A simple script can look like: #!/bin/csh -f mkdir $1; cd $1 ; git clone git://git.code.sf.net/p/uvm/code ; cd code ; git branch --track $1 origin/$1 ; git checkout $1 ; By passing in your branch name to the script it will checkout that particular branch for you. git_uvm.csh UVM_1_2 ; You can give feedback via your Accellera representation or local EDA person or provide feedback here. Time is of the essence so act today. thanks,