paul Posted June 21, 2011 Report Share Posted June 21, 2011 hello, I have a register model describing register with various size 16bits, 32 bits or 128 bits. In my uvm_reg_block this registers are well defined but when I tried to access the 128 bits register the data width of the transaction is only 32 bits instead of 128. Futhermore, this issue happened only if the address of my 128 bits register is higher than my 32 bits register. Would anyone have a rational explanation Quote Link to comment Share on other sites More sharing options...
uwes Posted June 22, 2011 Report Share Posted June 22, 2011 hello,I have a register model describing register with various size 16bits, 32 bits or 128 bits. In my uvm_reg_block this registers are well defined but when I tried to access the 128 bits register the data width of the transaction is only 32 bits instead of 128. Futhermore, this issue happened only if the address of my 128 bits register is higher than my 32 bits register. Would anyone have a rational explanation hi, did you extend `UVM_REG_DATA_WIDTH to 128? otherwise your reg fields can only store upto 64bits by default. /uwe Quote Link to comment Share on other sites More sharing options...
paul Posted June 22, 2011 Author Report Share Posted June 22, 2011 Hello, I did! I also find the origin of my problem. In fact in my regmodel I made a mistake by declaring : default_map = create_map("default_map", 'h6F80000, 4, UVM_BIG_ENDIAN, 0); instead of: default_map = create_map("default_map", 'h6F80000, 16, UVM_BIG_ENDIAN, 0); thanks you Quote Link to comment Share on other sites More sharing options...
Amy98 Posted March 16, 2022 Report Share Posted March 16, 2022 On 6/21/2011 at 1:56 AM, paul said: hello, I have a register model describing register with various size 16bits, 32 bits or 128 bits. In my uvm_reg_block this registers are well defined but when I tried to access the 128 bits register the data width of the transaction is only 32 bits instead of 128. Futhermore, this issue happened only if the address of my 128 bits register is higher than my 32 bits register. Would anyone have a rational explanation Hi Paul I have the same error as register model requires that UVM_REG_DATA_WIDTH be defined as 256 or greater. Currently defined as 64. How to change from 64 value ? Thanks Quote Link to comment Share on other sites More sharing options...
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