krb Posted May 18, 2011 Report Share Posted May 18, 2011 Hi, Anyone using SystemVerilog UVM with SystemC ? We have our reference models in SystemC, these models have fifo and other components. Basically they work in blocking put port way. I would like to know how the other uvm users are mixing System Verilog with System C ? I know of two options, using DPI-SC and ml_uvm, and unfortunately none of them are standards. Thanks, krb Quote Link to comment Share on other sites More sharing options...
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