Command Line usage

jsree · May 13, 2011

Hi

How to use Command Line to set some values inside uvm_object or sequence_lib

Created a sequence_lib and added few sequence.

I like to change min_random_count, max_random_count, sequence_count from the command line.

Plus my QS, to set this I need add config_db get function to my sequence_lib ?

the sequence lib : uvm_test_top.demo_tb0.tm.simple_tx_agent.sequencer@@simple_seq_lib

followig cmd_line_args will work ?

+uvm_set_config_int=uvm_test_top.demo_tb0.tm.simple_tx_agent.sequencer@@simple_seq_lib,sequence_count,5

Thanks

Jay

uwes · May 16, 2011

hi,

1. the set path should be by default "uvm_test_top.demo_tb0.tm.simple_tx_agent.sequencer.<typename-of-seq>.<fieldname>". you can find out the full path of your seqlib instance by printing get_full_name()

2. the handling of the standard fields of the seqlib require that the uvm_config_db is being used for the set. the reason for that is that the type specifier of "int unsigned" is used to pull the values from the config database. unfortunately this also means it has to be set using "int unsigned" which is incompatible with the bitstream_t which +uvm_set_config_int uses.

3. in order to resolve that you could in your seq lib reimplement m_get_config() and forward the config values set on uvm_config_db(uvm_bitstream_t){min_random_count, max_random_count, sequence_count } to uvm_config_db#(int unsigned) and then call the original via super.m_get_config

/uwe

jsree · May 16, 2011

Hi uwes

the answer was not very clear, However after reading UVM file: seq/uvm_sequence_library.svh which have following :

void'(uvm_config_db #(int unsigned)::get(m_sequencer,

phase_name,

"default_sequence.min_random_count",

min_random_count) );

void'(uvm_config_db #(int unsigned)::get(m_sequencer,

phase_name,

"default_sequence.max_random_count",

max_random_count) );

tried with commandline option

+uvm_set_config_int=uvm_test_top.demo_tb0.tm.simple_tx_agent.sequencer.main_phase,default_sequence.min_random_count,25 +uvm_set_config_int=uvm_test_top.demo_tb0.tm.simple_tx_agent.sequencer.main_phase,default_sequence.max_random_count,25

and expect to see 25 sequence and but saw only 10 sequence (which is default)

am i missing some thing ?

Thanks

Jay

uwes · May 17, 2011

hi,

maybe i didnt state it clear enough. the +uvm_set_config_int cmdline option maps the set to an set_config_int (and finally to uvm_config_db#(uvm_bitstream_t)::*) HOWEVER the code in uvm_sequence_library is accessing the config db with a uvm_config_db#(int unsigned)::*. as these two types are NOT equivalent the standard implementation cant see values set using the cmdline facility.

i opened a mantis for this http://eda.org/svdb/view.php?id=3560

one workaround is to "copy" over the values from the uvm_config_db(uvm_bitstream_t) to uvm_config_db(int unsigned) prior to a call to uvm_sequence_library.m_get_config

/uwe

jsree · May 17, 2011

Hi uwes,

Thanks and Now it is clear. Could you please provide a sample code for workaround too.

Warm regards

Jay

uwes · May 18, 2011

hi,

here we go:

class my_seq_lib extends uvm_sequence_library #(my_item_c);
   `uvm_object_utils(my_seq_lib) 
   `uvm_sequence_library_utils(my_seq_lib)
   function new(string name="my_seq_lib"); 
       super.new(name); 
       init_sequence_library();
   endfunction

   virtual task body();
       string phase_name;
       if (starting_phase != null) begin
           phase_name = {starting_phase.get_name(),"_phase"};
       end

       void'(uvm_config_db#(uvm_bitstream_t)::get(m_sequencer, 
           phase_name,
           "default_sequence.min_random_count",
           min_random_count)) ;


       void'(uvm_config_db #(uvm_bitstream_t)::get(m_sequencer, 
               phase_name,
               "default_sequence.min_random_count",
               min_random_count) );

       void'(uvm_config_db #(uvm_bitstream_t)::get(m_sequencer, 
               phase_name,
               "default_sequence.max_random_count",
               max_random_count) );

       void'(uvm_config_db #(uvm_bitstream_t)::get(m_sequencer, 
               phase_name,
               "default_sequence.selection_mode",
               selection_mode) );

       super.body();
   endtask
endclass

now you can use a cmdline setting like

+uvm_set_config_int=uvm_test_top.tb.sequencer,default_sequence.max_random_count,33

Edited May 18, 2011 by uwes

jsree · May 18, 2011

Hi Owes

Thanks and let me try this.

Jay

jsree · May 18, 2011

Hi Owes

the min_random_count and max_random_counts are int unsigned, config_db unable to assign from uvm_bitstream_t to int unsigned.

compile Error: (cadence simulator)

ncelab: *W,BNDWRN (./uvmpl/svpl/svpl_seg_c3eli_d_class.sv,206|19): Bit-select or part-select index out of declared bounds [4.2.1(IEEE)].
           min_random_count)) ;
                          |
ncelab: *E,TYCMPAT (./uvmpl/pkt_lib_sequences.sv,207|26): ref formal and actual do not have equivalent data types (expecting datatype compatible with 'signed packed array [4095:0] of logic' but found 'int' instead).
               max_random_count) );
                              |
ncelab: *E,TYCMPAT (./uvmpl/pkt_lib_sequences.sv,212|30): ref formal and actual do not have equivalent data types (expecting datatype compatible with 'signed packed array [4095:0] of logic' but found 'int' instead).
               selection_mode) );
                            |
ncelab: *E,TYCMPAT (./uvmpl/pkt_lib_sequences.sv,217|28): ref formal and actual do not have equivalent data types (expecting datatype compatible with 'signed packed array [4095:0] of logic' but found 'uvm_sequence_lib_mode' instead).
irun: *E,ELBERR: Error during elaboration (status 1), exiting

the VCS compie Error

Error-[IRPC] Illegal ref port connection
./uvmpl/pkt_lib_sequences.sv, 204
uvm_pkg, "this.min_random_count"
  Illegal connection to the ref port 'value' of function/task/module 
  'uvm_config_db_0::get'.


Error-[IRPC] Illegal ref port connection
./uvmpl/pkt_lib_sequences.sv, 209
uvm_pkg, "this.max_random_count"
  Illegal connection to the ref port 'value' of function/task/module 
  'uvm_config_db_0::get'.


Error-[IRPC] Illegal ref port connection
./uvmpl/pkt_lib_sequences.sv, 214
uvm_pkg, "this.selection_mode"
  Illegal connection to the ref port 'value' of function/task/module 
  'uvm_config_db_0::get'.

Modified the task body :

virtual task body();
       uvm_bitstream_t min_cnt, max_cnt;
       string phase_name;
       if (starting_phase != null) begin
           phase_name = {starting_phase.get_name(),"_phase"};
       end


      min_cnt = min_random_count;
      max_cnt = max_random_count;

       void'(uvm_config_db #(uvm_bitstream_t)::get(m_sequencer,
           phase_name,
           "default_sequence.min_random_count",
           min_cnt)) ;

       void'(uvm_config_db #(uvm_bitstream_t)::get(m_sequencer,
               phase_name,
               "default_sequence.max_random_count",
               max_cnt) );
/*
       void'(uvm_config_db #(uvm_bitstream_t)::get(m_sequencer,
               phase_name,
               "default_sequence.selection_mode",
               selection_mode) );
*/
        min_random_count = min_cnt;
        max_random_count = max_cnt;
       super.body();
   endtask

Now no compilation issue, command line args are as follows

+uvm_set_config_int=uvm_test_top.demo_tb0.csco_tm.simple_tx_agent\*,default_sequence.min_random_count,11 +uvm_set_config_int=uvm_test_top.demo_tb0.csco_tm.simple_tx_agent.\*,default_sequence.max_random_count,11

if min and max count value is not 10, the solver fails in both simulator

Solver failed when solving following set of constraints 


bit[0:0] is_randomized = 1'h1;
bit[31:0] sequences.size() = 32'h6;
bit[15:0] select_randc = 16'h0;
bit[31:0] sequence_count = 32'ha;
bit[31:0] min_random_count = 32'hb;
bit[31:0] max_random_count = 32'hb;

constraint valid_sequence_count    // (from this) (constraint_mode = ON) (<uvm_sequence_library.svh>:236)
{
    (  sequence_count  inside  {  [  min_random_count  :  max_random_count  ]  }  ) ;
}

=======================================================


Error-[CNST-CIF] Constraints inconsistency failure
uvm_sequence_library.svh, 699
  Constraints are inconsistent and cannot be solved.
  Please check the inconsistent constraints being printed above and rewrite 
  them.

I am still debugging to fix this.

Jay

uwes · May 19, 2011

hmmm,

interesting, the code has been run on IUS-10.20s40 without issues... which version do you use?

(i know that the line with selection_mode is violating the enum assignment rules in sv)

jsree · May 20, 2011

Hi Owes

Jay

jadec · May 20, 2011

The sequence_lib will be randomized before it's body is executed. You'd have to do the get in the constructor.

uwes · May 23, 2011

hi,

the error is (probably) not related to the problem of contructor or not althrough i agree the better place is the constructor.

/uwe

Command Line usage

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