reedzhu Posted May 3, 2011 Report Share Posted May 3, 2011 (edited) We encounter a simulation error as following when porting OVM to UVM: In our testbench we use a parameter virtual sequencer which includes several sequencers, and a parameter virtual sequence which is the base class of various sub virtual sequencers. We use `uvm_declare_p_sequencer(pcie_virtual_sequencer #(IF_PARAMS)) in the base virtual sequence(pcie_virtual_seq_base) to declear p_sequencer. But when simulation starts there is an error reported as following: UVM_FATAL uvm_test_top.env.virtual_sequencer@@<unknown> [DCLPSQ] xxx::pcie_virtual_seq_base.m_set_p_sequencer uvm_test_top.env.virtual_sequencer.<unknown> Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer It seems the member object m_sequencer of pcie_virtual_seq_base can’t be converted to the parameter virtual sequencer pcie_virtual_sequencer. The code is OK in OVM version. And I changed some items for UVM: 1. replace `uvm_sequencer_utils by `uvm_component_utils 2. remove `uvm_update_sequence_lib 3. replace set_config_string("*", "default_sequence".... by uvm_config_db#(uvm_object_wrapper)(.. In test case, I create a sub-sequence driverd from pcie_virtual_seq_base and use req.start() to launch tese in run_phase. could anyone give me some advise? Thanks! Edited May 3, 2011 by reedzhu Quote Link to comment Share on other sites More sharing options...
uwes Posted May 4, 2011 Report Share Posted May 4, 2011 hi, you can check in the GUI the types of m_sequencer and p_sequencer and see if there is a mismatch in the parameter set. apart from this you would need to provide more details about your sequencer types/instances etc. /uwe Quote Link to comment Share on other sites More sharing options...
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