loglong Posted March 21, 2011 Report Share Posted March 21, 2011 Hi, I have derive the virtual sequencer class from the uvm_sequencer class class uart_tb_vsd extends uvm_sequencer; but it reported syntax error as: *E,SVNOTY (/home/gendaili/projects/uvm_tb/verif/sv/uart_tb_vsd.sv,4|38): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope. ------ In SystemVerilog syntax, if a datatype begins with an identifier, the identifier must refer to a type. Make sure that the typedef of the desired type is visible in that scope or that there are not multiple wild card import clauses importing typedefs of the same identifier name. The latter would make the use of a simple type name ambiguous; in that case, in order to disambiguate which type is desired you must provide a full type name of the form package_name::type_name. What's wrong with it? is it require a specific sequence item like: class uart_tb_vsd extends uvm_sequencer #(uart_transfer) ; Please help me out, thanks. Quote Link to comment Share on other sites More sharing options...
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