rafael.shirakawa Posted March 7, 2011 Report Share Posted March 7, 2011 Inside a uvm_env class, I try to create an array of another uvm_env class. I need to pass parameters to each element of this array. I can't use a generate loop inside the class and I couldn't find out a way to use a for loop to pass the individual parameters. My last attempt was to declare an array of class inside my uvm_env class like: class_type1 class_array [9:0]; and then to pass the parameters at the module where this class is, by using 'defparam' inside a generate: module ... ... genvar i; generate for (i=0 ; i<=9 ; i++) begin defparam class_instance.class_array.param = my_params; end endgenerate ... endmodule But the compiler then complains that I use the class (already with parameters) in the build phase. I'm using a for loop in the build function to loop through all elements. Is there a way to create an array of parameterized classes inside a class in systemverilog? Quote Link to comment Share on other sites More sharing options...
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