Data sampling in SC?

[Dhaval_Shah_]

Hi,

 

I have 3 components in system. Two in SC [Tx and Rx] and One in SV.

Two SC modules are connected in sc_main which is exported. SV is connected via UVM Connect.

 

Tx is driving clock and few signals to Rx. Rx is sampling signals on posedge of clock driven by Tx.

SV component is also sampling same set of signals on posedge of clock which is driven by Tx.

 

Tx is driving clock via sc_out<bool> and Rx is receiving clock via sc_in<bool>.

 

Problem is when Tx drives some signals on posedge of clock, Rx receives change in signals at the same time....where as SV component sees same change on next posedge.

 

Q - Is this how SC/SV event scheduler is expected?

Q - If not then what is the remedy?

 

Dhaval

[apfitch]

What you've described in SystemC sounds like expected behaviour - if you drive the clock and the signals at the same instant in the transmitter, then the receiver module will detect the clock and see the updated values of the signals - if I've understood you correctly.

 

Regarding connecting to SV, there's no standardisation of how multi-language simulation should behave, so you need to read your simulator documentation,

 

regards

Alan

[Dhaval_Shah_]

Thank Alan.

Instead of driving clock from Tx, I connected clock of both Tx and Rx from top module. Its working then after.

I dont know, how does it make difference for Rx in this case.

 

Dhaval

[apfitch]

Hi Dhaval,

 what you're describing is just standard synchronous design good practice.

 

Instant summary: ideally all blocks have a common clock, communication between blocks uses signals; signals follow evaluate/update semantics, which guarantees that you always see the current value of a signal, not the future value. Hence no race hazards/hold time violations.

 

regards

Alan