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  1. Thank Alan. Instead of driving clock from Tx, I connected clock of both Tx and Rx from top module. Its working then after. I dont know, how does it make difference for Rx in this case. Dhaval
  2. Hi, I have 3 components in system. Two in SC [Tx and Rx] and One in SV. Two SC modules are connected in sc_main which is exported. SV is connected via UVM Connect. Tx is driving clock and few signals to Rx. Rx is sampling signals on posedge of clock driven by Tx. SV component is also sampling same set of signals on posedge of clock which is driven by Tx. Tx is driving clock via sc_out<bool> and Rx is receiving clock via sc_in<bool>. Problem is when Tx drives some signals on posedge of clock, Rx receives change in signals at the same time....where as SV component s
  3. Hi, I am trying to connect SV-SC ports via UVMC and while sccom -link I am getting below error. I am running simulation in windows. Using UVM-1.0p and UVMC-2.2. Individual compilation of SV and SC is clean with UVMC-2.2 but problem when linking them. Can anyone suggest a solution? Dhaval # work\_sc\win32_gcc-4.2.1\sc_main.o:sc_main.cpp:(.text$_ZN4uvmc21uvmc_initiator_socketILj32EN3tlm23tlm_base_protocol_typesELi1ELN7sc_core14sc_port_policyE0E14uvmc_converterINS1_19tlm_generic_payloadEEE15nb_transport_bwERS6_RNS1_9tlm_phaseERNS3_7sc_timeE[uvmc::uvmc_initiator_socket<32u, tlm::tlm_base_p
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