Jump to content

UVM test simulation using vcs and DVE


Recommended Posts

Hi,

I am a beginner ..

I wrote a simple UVM verification environment using the uvm-1.2 examples, and could compile and run it but I could not see any wave form.

the run command : simv +UVM_STACKRACE +UVM_TESTNAME=test_base -l run.log -gui

in the run.log I could see that the simulation time is 1000ps

how can I see the waveform (want to check if the clock and reset signals were correctly operated)???

 

thanks a lot 

 

 

Link to comment
Share on other sites

  • 4 months later...

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...