uvm_rookie Posted March 2, 2011 Report Share Posted March 2, 2011 UVM1.0 has an ubus example. One of the test has the following code. Instead of using set_config_string, we need to use uvm_config_db .. We do this in the build phase of this test class. How come we need to use "sequencer.run_phase", instead of "sequencer.build_phase" ? // Read Modify Write Read Test class test_read_modify_write extends ubus_example_base_test; `uvm_component_utils(test_read_modify_write) function new(string name = "test_read_modify_write", uvm_component parent=null); super.new(name,parent); endfunction : new virtual function void build_phase(uvm_phase phase); begin uvm_config_db#(uvm_object_wrapper)::set(this, "ubus_example_tb0.ubus0.masters[0].sequencer.run_phase", "default_sequence", read_modify_write_seq::type_id::get()); uvm_config_db#(uvm_object_wrapper)::set(this, "ubus_example_tb0.ubus0.slaves[0].sequencer.run_phase", "default_sequence", slave_memory_seq::type_id::get()); // Create the tb super.build_phase(phase); end endfunction : build_phase endclass : test_read_modify_write Quote Link to comment Share on other sites More sharing options...
uwes Posted March 2, 2011 Report Share Posted March 2, 2011 hi, the ::set operation sets the default sequence (the one which is automatically started) for a particular phase. so basically you "configure" during build_phase() that a particular sequence should automatically run in the "run_phase()". btw the build_phase() is not a run_time phase and would therefore not execute any sequences. Quote Link to comment Share on other sites More sharing options...
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