kavin@atrialogic.com Posted January 23, 2015 Report Share Posted January 23, 2015 Hello All , I am a beginner in SystemC with Hardware verification background (sv/uvm). I coded a simple synchronous design (sensitive_pos (clk)) and ran the simulation using questasim10.2 . Sadly In waveform the behavior looked as a combination logic rather than a sequential one. Whether its the problem of simulator or systemc ? .Also what will be the best simulator for SystemC. Thanks in advance, Kavinkumar (MTS , AtriaLogic). Quote Link to comment Share on other sites More sharing options...
apfitch Posted January 23, 2015 Report Share Posted January 23, 2015 It's almost definitely a problem with your code. Questa definitely works. As does the Proof of Concept simulator you can download for free from Accellera. The best simulator depends on your criteria. The lowest cost simulator is the free download - but of course you don't get nice integrated debugging and waveform viewing. If you want a better debugging environment, then you're better off using Questa, or Incisive, or VCS, or Riviera: but it will cost you. regards Alan P.S. sensitive_pos is deprecated, you should use sensitive << clk.pos() Quote Link to comment Share on other sites More sharing options...
kavin@atrialogic.com Posted January 24, 2015 Author Report Share Posted January 24, 2015 Thanks Alan will change the senstivity and see Quote Link to comment Share on other sites More sharing options...
kavin@atrialogic.com Posted January 24, 2015 Author Report Share Posted January 24, 2015 #include "systemc.h"SC_MODULE (singleport_ram){ sc_in<bool> clk; sc_in<bool> rd; sc_in<bool> wr; sc_in<sc_uint< 9> > wr_address; sc_in<sc_uint< 9> > rd_address; sc_in<sc_uint<32> > data_in; sc_out<sc_uint<32> > data_out; sc_out<bool> vld; sc_lv <32> mem [512]; void mem_wr (); void mem_rd (); SC_CTOR (singleport_ram) { SC_METHOD (mem_wr); sensitive << clk.pos(); SC_METHOD (mem_rd); sensitive << clk.pos(); }};void singleport_ram :: mem_rd () { if (rd.read()) { data_out.write (mem [rd_address.read()]); vld.write( 1); } else { vld.write( 0); } }void singleport_ram :: mem_wr () { if (wr.read()) { mem [wr_address.read()] = data_in; } }; Alan can you point where i could have gone wrong? Thanks kavin Quote Link to comment Share on other sites More sharing options...
apfitch Posted January 24, 2015 Report Share Posted January 24, 2015 That looks good to me. What is wrong with the waveforms? One issue that can catch you out is the time resolution of the simulator, the speed of your clock, and the time resolution of the waveforms. I guess if you're using Questa, you're using the built-in waveform tracing (not using your own vcd trace file). Questa will probably default to a resolution of either 1ns or 1ps. So I would check the clock frequency in your testbench to make sure it is sensible (much bigger than 1ns, say 10ns) regards Alan Quote Link to comment Share on other sites More sharing options...
kavin@atrialogic.com Posted January 25, 2015 Author Report Share Posted January 25, 2015 Yes , I am using Questa's default wave , dint use any tracers , i have used clock cycle as 10ns . Let me make clock cycle larger and see the resulting wave . Thanks for your time Alan Quote Link to comment Share on other sites More sharing options...
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