kavin@atrialogic.com

Yes , I am using Questa's default wave , dint use any tracers , i have used clock cycle as 10ns . Let me make clock cycle larger and see the resulting wave . Thanks for your time Alan

#include "systemc.h" SC_MODULE (singleport_ram) { sc_in<bool> clk; sc_in<bool> rd; sc_in<bool> wr; sc_in<sc_uint< 9> > wr_address; sc_in<sc_uint< 9> > rd_address; sc_in<sc_uint<32> > data_in; sc_out<sc_uint<32> > data_out; sc_out<bool> vld; sc_lv <32> mem [512]; void mem_wr (); void mem_rd (); SC_CTOR (singleport_ram) { SC_METHOD (mem_wr); sensitive << clk.pos(); SC_METHOD (mem_rd); sensitive << clk.pos(); } }; void singleport_ram :: mem_rd () { if (rd.read()) { data_out.write (mem [rd_address.read()]); vld.write( 1); } else { vld.write( 0); } } void singleport_ram :: mem_wr () { if (wr.read()) { mem [wr_address.read()] = data_in; } }; Alan can you point where i could have gone wrong? Thanks kavin

Thanks Alan will change the senstivity and see

Hello All , I am a beginner in SystemC with Hardware verification background (sv/uvm). I coded a simple synchronous design (sensitive_pos (clk)) and ran the simulation using questasim10.2 . Sadly In waveform the behavior looked as a combination logic rather than a sequential one. Whether its the problem of simulator or systemc ? .Also what will be the best simulator for SystemC. Thanks in advance, Kavinkumar (MTS , AtriaLogic).