vsreeniv Posted January 5, 2015 Report Share Posted January 5, 2015 Hi I am thinking of moving from verilog to systemc for hardware design. I have a question about sensitivity list: When I am implementing a logic cloud (not clocked) in verilog, I use the "always @* begin" construct to ensure that all the inputs are in the sensitivity list. Is there a similar construct in systemc, where I don't have to explicitly list all the inputs that can cause the output to change? thanks, Venkat. Quote Link to comment Share on other sites More sharing options...
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