KARTHIKEYAN Posted December 5, 2014 Report Share Posted December 5, 2014 hai to all Iam karthik,doing my masters in VLSI DESIGN ,i found my interest in system level design and i wish to do project in systemcTLM based simulation.As a starter ,learning systemC language and i want to learn how systemc TLM differ by verilog,VHDL and other languages by results.i.e by simulation...kindly guide me regarding by suggesting some projects or papers in these domains.. keywords:co-simulation,systemc based simulations.. Quote Link to comment Share on other sites More sharing options...
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