rashmikant.nu@gmail.com Posted December 4, 2014 Report Share Posted December 4, 2014 Hi All, I am using system verilog constraints framework to randomize bunch of registers for my design. Each register has few register fields & all of them are declared as a 'rand' variables. In below case, in my original source-code of constraints, I have declared ABC as 'rand' variable along with XYZ variable. However, when the constraints are getting solved, at the state of failure, ABC is given a value of 1'h1. even though my source code says, 'solve Reg1.XYZ before Reg2.ABC' ---------- Source-code: ---- solve Reg1.XYZ before Reg2.ABC; Reg1.XYZ.value == 0; if(Reg1.XYZ.value == 0) Reg2.ABC.value == 0; ---- Error:: ------- Solver failed when solving following set of constraints bit[0:0] Reg2.ABC.value = 1'h1; rand bit[1:0] Reg1.XYZ.value; // rand_mode = ON constraint c_RandomizeReg2.ABCType // (from (constraint_mode = ON) (rndcfg_constraints_def_gen.sv:3063) { (Reg1.XYZ.value == 2'h0); (Reg1.XYZ.value == 2'h0) -> (Reg2.ABC.value == 1'h0); } ----------- In the above failure, what I am confused about is that why is VCS fixing value of Reg2.ABC set to 1'h1 when value of Reg1.XYZ is not yet assigned even though I have a line which says 'solve .. before ...' I am using below VCS version: ---------- Chronologic VCS simulator copyright 1991-2013 Contains Synopsys proprietary information. Compiler version H-2013.06-SP1-10; Runtime version H-2013.06-SP1-10; Dec 4 13:48 2014 ---------------- I don't have any hardcoding done in my code which forces ABC to be value of 1. Another observation I made is, if I do a command-line force of ABC register field to be value of '0', it will pass the constraint as expected giving me the intended result. However when I let the simulator pick the value, it doesn't solve the constraint. Can someone please throw light on how can I go about debugging why is the simulator setting the value of ABC & not honoring solve-before. thanks, -Rashmi Quote Link to comment Share on other sites More sharing options...
apfitch Posted December 4, 2014 Report Share Posted December 4, 2014 It's hard to say, but VCS seems to be saying that Reg2.ABC.value is not declared rand? (i.e. the value member of the ABC class is not declared rand). Alan Quote Link to comment Share on other sites More sharing options...
rashmikant.nu@gmail.com Posted December 5, 2014 Author Report Share Posted December 5, 2014 Thanks for the reply Alan. Actually, 'value' is not a field inside ABC. ABC itself is a field inside Reg2. The only way the VCS lets me assign or reference values 'placed' on random variables is by doing FIELD.value. Quote Link to comment Share on other sites More sharing options...
apfitch Posted December 7, 2014 Report Share Posted December 7, 2014 That still sounds odd to me. "value" is a data member in the uvm_reg_field class. If you set the field to be e.g. RO, then it won't be randomized. See this code from uvm_reg_field.svh // Ignore is_rand if the field is known not to be writeable // i.e. not "RW", "WRC", "WRS", "WO", "W1", "WO1" case (access) "RO", "RC", "RS", "WC", "WS", "W1C", "W1S", "W1T", "W0C", "W0S", "W0T", "W1SRC", "W1CRS", "W0SRC", "W0CRS", "WSRC", "WCRS", "WOC", "WOS": is_rand = 0; endcase if (!is_rand) value.rand_mode(0); What types are ABC and Reg2? Alan Quote Link to comment Share on other sites More sharing options...
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