I am using system verilog constraints framework to randomize bunch of registers for my design. Each register has few register fields & all of them are declared as a 'rand' variables.
In below case, in my original source-code of constraints, I have declared ABC as 'rand' variable along with XYZ variable. However, when the constraints are getting solved, at the state of failure, ABC is given a value of 1'h1. even though my source code says,
'solve Reg1.XYZ before Reg2.ABC'
solve Reg1.XYZ before Reg2.ABC;
Reg1.XYZ.value == 0;