Jump to content

multiple SystemC tops in UVM_ML

Recommended Posts

It seems an unrelated warning. TPREGD is a UVM SystemVerilog message while you're asking about multiple SystemC top uvm_components/modules.


There should be no problem to specify multiple SystemC top components because you are providing two different types: top1_sc and top2_sc.

I'm assuming here that those are SystemC module or uvm_component names.


Link to comment
Share on other sites

  • 2 weeks later...

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

  • Create New...