matteodc Posted November 27, 2014 Report Share Posted November 27, 2014 Hello, Can I do this? tops[0] = "SC:top1_sc"; tops[1] = "SC:top2_sc"; tops[2] = "SV:dut"; uvm_ml_run_test(tops, ""); Thanks Quote Link to comment Share on other sites More sharing options...
matteodc Posted November 27, 2014 Author Report Share Posted November 27, 2014 Apparently not: reporter [TPRGED] Type name 'a_b' already registered with factory. No string-based lookup support for multiple types with the same type name. Quote Link to comment Share on other sites More sharing options...
vitalyya Posted November 27, 2014 Report Share Posted November 27, 2014 It seems an unrelated warning. TPREGD is a UVM SystemVerilog message while you're asking about multiple SystemC top uvm_components/modules. There should be no problem to specify multiple SystemC top components because you are providing two different types: top1_sc and top2_sc. I'm assuming here that those are SystemC module or uvm_component names. Quote Link to comment Share on other sites More sharing options...
matteodc Posted December 10, 2014 Author Report Share Posted December 10, 2014 Hi, There is no problem, you are right. It works fine. Yes,they are SystemC modules. Quote Link to comment Share on other sites More sharing options...
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