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multiple SystemC tops in UVM_ML


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It seems an unrelated warning. TPREGD is a UVM SystemVerilog message while you're asking about multiple SystemC top uvm_components/modules.


There should be no problem to specify multiple SystemC top components because you are providing two different types: top1_sc and top2_sc.

I'm assuming here that those are SystemC module or uvm_component names.


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