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matteodc

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Everything posted by matteodc

  1. Hi, have a look here: http://www.cplusplus.com/reference/vector/vector/ http://www.cplusplus.com/reference/algorithm/find_if/
  2. Hi, http://www.microsoft.com/en-us/download/details.aspx?id=23205 This is the standalone profiler for VS2010 Professional.
  3. Have you run a benchmark or profiled your code?
  4. I would prefer an object oriented approach, i.e. a base class to implement common functionality and derived classes for specialization. Then, depending on the uvm_test randomization, type substitution by using the UVM factory. This approach reduces the code changes required in some scenarios. Regards
  5. Hi Yuval, thank you very much for your reply. I came up with a similar solution by converting the sc_fixed to an integer and packing it, but yours it is more elegant. I don't need to send data from the SV to the SC, so I ignored the do_unpack. Best Regards
  6. Hi, I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed. virtual uvm_packer& operator << (bool a); virtual uvm_packer& operator << (char a); virtual uvm_packer& operator << (unsigned char a); virtual uvm_packer& operator << (short a); virtual uvm_packer& operator << (unsigned short a); virtual uvm_packer& operator << (int a); virtual uvm_packer& operator << (unsigned int a); virtual uvm_packer& operator << (long a); virtual uvm_packer& operator << (unsigned long a); virtual uvm_packer& operator << (long long a); virtual uvm_packer& operator << (unsigned long long a); virtual uvm_packer& operator << (std::string a); virtual uvm_packer& operator << (const char*); virtual uvm_packer& operator << (uvm_object* a); virtual uvm_packer& operator << (const uvm_object& a); virtual uvm_packer& operator << (const sc_logic& a); virtual uvm_packer& operator << (const sc_bv_base& a); virtual uvm_packer& operator << (const sc_lv_base& a); virtual uvm_packer& operator << (const sc_int_base& a); virtual uvm_packer& operator << (const sc_uint_base& a); virtual uvm_packer& operator << (const sc_signed& a); virtual uvm_packer& operator << (const sc_unsigned& a); template <class T> Any idea how to solve it? Thanks
  7. Hi, I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed. virtual uvm_packer& operator << (bool a); virtual uvm_packer& operator << (char a); virtual uvm_packer& operator << (unsigned char a); virtual uvm_packer& operator << (short a); virtual uvm_packer& operator << (unsigned short a); virtual uvm_packer& operator << (int a); virtual uvm_packer& operator << (unsigned int a); virtual uvm_packer& operator << (long a); virtual uvm_packer& operator << (unsigned long a); virtual uvm_packer& operator << (long long a); virtual uvm_packer& operator << (unsigned long long a); virtual uvm_packer& operator << (std::string a); virtual uvm_packer& operator << (const char*); virtual uvm_packer& operator << (uvm_object* a); virtual uvm_packer& operator << (const uvm_object& a); virtual uvm_packer& operator << (const sc_logic& a); virtual uvm_packer& operator << (const sc_bv_base& a); virtual uvm_packer& operator << (const sc_lv_base& a); virtual uvm_packer& operator << (const sc_int_base& a); virtual uvm_packer& operator << (const sc_uint_base& a); virtual uvm_packer& operator << (const sc_signed& a); virtual uvm_packer& operator << (const sc_unsigned& a); template <class T> Any idea how to solve it? Thanks
  8. I have removed SC_THREAD and added a wait() in the put method: virtual void put(const DATA_TYPE &t) { wait(); <- it stops here }; But I get, SC_REPORT_ERROR( SC_ID_WAIT_NOT_ALLOWED_, "\n " "in SC_METHODs use next_trigger() instead" ); break; } It is quite clear. If I add next_trigger(), I get: SC_REPORT_ERROR( SC_ID_NEXT_TRIGGER_NOT_ALLOWED_, "\n " "in SC_THREADs and SC_CTHREADs use wait() instead" ); } And this is the reason I put SC_THREAD.. How to solve it? Thanks
  9. Hi, when I try to do this: typedef tlm::tlm_blocking_put_if<DATA_TYPE> TLM_BUS_IF_TYPE; template < class M > class chan : public TLM_BUS_IF_TYPE, public sc_core::sc_channel { public: SC_HAS_PROCESS(chan); chan(sc_core::sc_module_name nm) : sc_core::sc_channel(nm) { SC_THREAD(put); }; virtual void put(const DATA_TYPE &t) { wait(m_delay); <- it stops here }; }; I get: error C2440: 'static_cast' : cannot convert from 'void (__thiscall E::chan<M>::* )(const E::DATA_TYPE &)' to 'sc_core::SC_ENTRY_FUNC' Any idea? Thanks
  10. Thanks David. Thanks Philipp, I moved the implementation of the interface inside a sc_channel, as I am reusing the same channel in multiple places. Now the code is similar to this: typedef std::vector<bool> DATA_TYPE; typedef tlm::tlm_blocking_put_if<DATA_TYPE> TLM_BUS_IF_TYPE; typedef sc_core::sc_export< TLM_BUS_IF_TYPE > TARGET_PORT_TYPE; typedef sc_core::sc_port< TLM_BUS_IF_TYPE, 0, SC_ZERO_OR_MORE_BOUND > INITIATOR_PORT_TYPE; ... SC_MODULE(E_top) { public: TARGET_PORT_TYPE in_port; INITIATOR_PORT_TYPE out_port; SC_CTOR(E_top) : in_port("input_port"), out_port("output_port"), p_e(new e), m_chan("chan",p_e, &out_port) { in_port.bind(m_chan); } private: boost::shared_ptr<e> p_e; chan<e> m_chan; //!SystemC Channel }; You are right, I will change the DATA_TYPE to be something else. Thanks Regards
  11. Hi, This is the macro: #define SC_CTOR(user_module_name) \ typedef user_module_name SC_CURRENT_USER_MODULE; \ user_module_name( ::sc_core::sc_module_name ) you can use a standard constructor instead of the macro: typedef TaskA SC_CURRENT_USER_MODULE; TaskA(sc_core::sc_module_name name) : sc_module (name), b ("base") { } For your error: When you declare a non-default constructor for a class, the compiler does not generate a default one anymore. So you have to provide your own.
  12. Ok, I have added this channel: class chan : public tlm::tlm_blocking_put_if<std::vector<bool>, public sc_core::sc_channel { public: chan(sc_core::sc_module_name nm) : sc_core::sc_channel(nm) {}; virtual void put(const std::vector<bool> &t) { m_payload=t; }; private: std::vector<bool> m_payload; }; and I have bound it in the C_top sc_module constructor: in_port(m_C_top.in_port); It works fine. Is this the correct way? Thanks
  13. Hi, I have two sc_module s both with an sc_export, templated with tlm::tlm_blocking_put_if<std::vector<bool> > . I connect the upper level sc_export to the lower level one, in the constructor of the sc_module. class E_top : sc_core::sc_module, tlm::tlm_blocking_put_if<std::vector<bool> { public: sc_export< tlm::tlm_blocking_put_if<std::vector<bool> > > in_port; E_top(sc_core::sc_module_name name) : sc_module ( name), in_port("input_port"), m_C_top("c") { m_payload.reserve(8); m_C_top.in_port(in_port); <--it stops here } virtual void put(const std::vector<bool> &t) { m_payload=t; in_port->put(m_payload); }; private: C_top m_C_top; std::vector<bool> m_payload; }; I guess the interface is null, SC_ID_SC_EXPORT_HAS_NO_INTERFACE_ is a good hint: sc_export.h: operator IF& () { if ( m_interface_p == 0 ) { -> SC_REPORT_ERROR(SC_ID_SC_EXPORT_HAS_NO_INTERFACE_,name()); } return *m_interface_p; } How to solve it? Thanks
  14. Hi, There is no problem, you are right. It works fine. Yes,they are SystemC modules.
  15. Apparently not: reporter [TPRGED] Type name 'a_b' already registered with factory. No string-based lookup support for multiple types with the same type name.
  16. Hello, Can I do this? tops[0] = "SC:top1_sc"; tops[1] = "SC:top2_sc"; tops[2] = "SV:dut"; uvm_ml_run_test(tops, ""); Thanks
  17. Hi Vitaly, it works fine now, thanks. Regards
  18. Hello, I have two classes in two different files: class B : public uvm_component { ... do_something(); ... } class A : public uvm_component { .... SetCallback(boost::bind(&B::do_something, *pB, _1, _2)); ... } When I try to compile this, I have this error: "/home/cadence/UVM_ML-1.3.4.3/ml/frameworks/uvm/sc/base/uvm_component.h", line 60: error: "sc_core::sc_module::sc_module(const sc_core::sc_module &)" (declared at line 398 of "$CDSROOT/tools/systemc/include_pch/64bi t/sysc/kernel/sc_module.h") is inaccessible class uvm_component : public sc_core::sc_module, public uvm_typed { ^ detected during: implicit generation of "uvm::uvm_component::uvm_component(const uvm::uvm_component &)" at line 14 of implicit generation of "collector::collector(const collector &)" at line 14 of Any idea? Thanks
  19. Hi, is it possible to change the type of a ml_tlm1 by using the UVM factory? Inside the UVC environment class: uvm_ml::ml_tlm1#(eq_transaction)::register(agent.monitor.in_port); In a test or in the testbench: factory.set_inst_override_by_type(eq_transaction::get_type(), dem_transaction::get_type(), {get_full_name(),"*.u_sym.env0.*"}); Thanks
  20. Was it a problem of multiple inheritance? Thanks Regards
  21. That's a very good question. I thought it was needed to use the port inside the class's method, i.e. Inside the write method of the sc_export I use: sc_output.write(sc_output_trans); Is it the right way? It compiles fine now. Thanks Regards
  22. Hello, I have this compile error: error: base class "tlm::tlm_analysis_if<sc_eq_pkg::eq_transaction>" is ambiguous dut_input.bind(*this); This is my code: using namespace tlm; using namespace sc_eq_pkg; class eq_wrapper_top : public uvm_component , tlm_analysis_if<eq_transaction> , tlm_analysis_port<eq_transaction> { public: sc_export<tlm_analysis_if<eq_transaction> > dut_input; // analysis export tlm_analysis_port<eq_transaction> sc_output; // analysis port //Inputs from transactions //Constructor eq_wrapper_top(sc_module_name nm) : uvm_component(nm) , dut_input("dut_input") , sc_output("sc_output") { dut_input.bind(*this); } Any idea? Thanks Regards
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