Segmentation fault with signal write

[rahuljn]

Hi Guys

 

I am getting the segmentation fault with following simple program, which I am not able to figure out why. Can you please help

 

#include "systemc.h"

class initiator : public sc_module {
    public:
    sc_signal<int> out;
    SC_HAS_PROCESS(initiator);
    initiator(sc_module_name name){
        SC_THREAD(process1);
        SC_THREAD(process2);
    }
    void process1(){
        wait(10,SC_NS);
        out.write(1);
    }
    void process2(){
        wait(1,SC_NS);
        out.write(0);
    }
};

int sc_main(int, char**){
    initiator* initiator_inst = new initiator("initiator");
    sc_start(100, SC_NS);
    return 0;
}

 

Can you please help.

 

Thanks

RahulJn

[ralph.goergen]

Hi,

 

a problem in your design is that you write to one signal from more than one process (multiple writers).

This is not allowed in the default sc_signal.

 

If you want to allow this, you can use the second template parameter of sc_signal to set the writer policy:

sc_signal<in, SC_MANY_WRITERS>

But you should be carefull with this. Multiple writers can lead to a number of problems and non-deterministec behaviour of the system.

 

The fact that SystemC runs into a segmentation fault instead of giving an error message seems to be a bug in SystemC.

 

Greetings

Ralph

[rahuljn]

Actually in my scenario one process is asserting a signal and other one has to dessert it after some delay. Can you tell me how to model this without using SC_MANY_WRITER

Thanks

[Philipp A Hartmann]

The fact that SystemC runs into a segmentation fault instead of giving an error message seems to be a bug in SystemC.

 

Yes, the segmentation fault is caused by trying to access the terminated process instance (to format the error message), which has been deleted already. This problem will be fixed in the next public release of the Accellera proof-of-concept implementation.

Thanks for your report,

  Philipp

[Philipp A Hartmann]

Actually in my scenario one process is asserting a signal and other one has to dessert it after some delay. Can you tell me how to model this without using SC_MANY_WRITER

 

Short answer: You can't. 

 

/Philipp

[rahuljn]

Thanks Philipp

btw, is there some other way to achieve this(assert/deassert)?

Thanks

Rahuljn

[Philipp A Hartmann]

btw, is there some other way to achieve this(assert/deassert)?

 

You can't let the second process write to the same signal (deassert) without using SC_MANY_WRITERS.

(This wouldn't make much sense in real HW without additional logic either.)

 

Solution: Restructure your design to have a single writer to each signal instead.

Hard to be more specific with the available details.

 

hth,

Philipp

[dakupoto]

Hi,

 

a problem in your design is that you write to one signal from more than one process (multiple writers).

This is not allowed in the default sc_signal.

 

If you want to allow this, you can use the second template parameter of sc_signal to set the writer policy:

sc_signal<in, SC_MANY_WRITERS>

But you should be carefull with this. Multiple writers can lead to a number of problems and non-deterministec behaviour of the system.

 

The fact that SystemC runs into a segmentation fault instead of giving an error message seems to be a bug in SystemC.

 

Greetings

Ralph

 

In my salad days, I ran into the issue of multiple writers a number of times,

but I always got runtime error messages. I have used SystemC 2.2, 2.3

and 2.3.1. Something else is not right.

As per the class definition, the processes are threads, and will run just

once each. So, even if one of the threads has finished execution, the

sc_signal is still intact(so long the module instance is not deleted) and

any other thread, if still not executed, should be able to write to it.

[rahuljn]

Hi Phillip

 

My real scenario is a Timer model with one TLM2 target port and one sc_out<bool> port for interrupt. The interrupts are level triggered.

Once the interrupt is generated and processed, sw need to write in interrupt clear register to deassert the interrupt port.

To test this timer model, I have a test bench with this timer and a traffic generator. In traffic generater, I have one TLM2 initiator socket and sc_in<bool> port. In traffic generator I have a thread process(P1) which program the counter register which in turn generates the interrupt after some time. I catch this interrupt in other thread process(P2) in same traffic generator.

In P1, I first programs the timer and than wait for an event from P2 and then I write on interrupt clear register to deassert the interrupt. 

In P2, I first wait for the interrupt and then wait for one cycle and then notify P1.

So I have two different threads writing on same signal(of course in different time)

 

Am I doing it right ?

Or there is some other good approach.

 

 

Thanks

RahulJn

[Philipp A Hartmann]

In your case, the Timer module (or a dedicated interrupt controller, wherever your "interrupt clear register" is located) would be responsible for actually writing to the interrupt signal.  This can then be locally resolved to a single control process within the module.

 

However, especially for interrupt signals, SC_MANY_WRITERS is a common use model.  Note that SC_MANY_WRITERS is perfectly safe to use, because you are still not allowed to write to a signal from multiple processes in the same delta cycle (as that could lead to non-deterministic behaviour).

 

/Philipp