About UVM function uvm_hdl_force

[jakfens]

 The UVM function uvm_hdl_force   format is 

uvm_hdl_force( string  path,   uvm_hdl_data_t  value )

 

My question is can I use a array path in the path?

 

For example :  uvm_hdl_force(  test_ben.cpu.block[0].instan[1].set[2] ,1 );

 

Can it work? Its compile is no problem.

 

Thank you very much~~

[uwes]

hi,

 

i think your problem isnt the example you show. as written test_ben.cpu.block[0].instan[1].set[2] must be a string and if this is the case the code should compile

For example :  uvm_hdl_force(  test_ben.cpu.block[0].instan[1].set[2] ,1 );

BUT the hard question is actually if the path argument 

 

A) refers to an instance path in the right language domain (SV,VHDL,SC,..) which the HDL backbone supports (might be vendor dependent)

from the vendor support and LRM for your path expression (does the string path involve slices, indices, addon levels via generics)

 

/uwe

[jakfens]

hi,

 

i think your problem isnt the example you show. as written test_ben.cpu.block[0].instan[1].set[2] must be a string and if this is the case the code should compile

For example :  uvm_hdl_force(  test_ben.cpu.block[0].instan[1].set[2] ,1 );

BUT the hard question is actually if the path argument 

 

A) refers to an instance path in the right language domain (SV,VHDL,SC,..) which the HDL backbone supports (might be vendor dependent)

from the vendor support and LRM for your path expression (does the string path involve slices, indices, addon levels via generics)

 

/uwe

hi , uwes

Thank you very much

Yes, your example is right.

The path language is Verilog and my env language is System Verilog.

There are many items in the array block[0], so do instan[1] and set[2].

So you mean my path is legal ?

Thank you for your regard