implementation verification using uvm

[swathi92]

suppose my design is having fifos,counters and logic for some complex algorithm.

using uvm i can create agents to test signals in interfaces.

how to verify internal fifos using uvm environment?

do i need to verify seperately?

[ejo]

suppose my design is having fifos,counters and logic for some complex algorithm.

using uvm i can create agents to test signals in interfaces.

how to verify internal fifos using uvm environment?

do i need to verify seperately?

 

One way to do this is binding a module with a monitor class to the fifo entity using the SV bind statement. This will instantiate the module underneath each instance of the fifo. Write a base class for the monitor in a package and have the factory new the actual monitor class in the bound module. The base class can provide ports, events etc for use by the sub-class in the bound module to communicate collected info. It could for example signal fifo-status via events and fifo-data via ports. Declaring the event and port members in the base class makes it easy to get hold of them in the connect phase, e.g. to connect them to receiving members of the scoreboard in order to compare collected data with the predicted, given input data to the algorithms in the design (and scoreboard). 

 

 

Erling

[swathi92]

 

One way to do this is binding a module with a monitor class to the fifo entity using the SV bind statement. This will instantiate the module underneath each instance of the fifo. Write a base class for the monitor in a package and have the factory new the actual monitor class in the bound module. The base class can provide ports, events etc for use by the sub-class in the bound module to communicate collected info. It could for example signal fifo-status via events and fifo-data via ports. Declaring the event and port members in the base class makes it easy to get hold of them in the connect phase, e.g. to connect them to receiving members of the scoreboard in order to compare collected data with the predicted, given input data to the algorithms in the design (and scoreboard). 

 

 

Erling

ejo can you please suggest any example for this so that i can get clear idea

[ejo]

ejo can you please suggest any example for this so that i can get clear idea

 

This thread may help. It shows how to communicate collected data from a design instance to a scoreboard via a port, but the data collector base could easily be extended with other data types (e.g uvm events to signal fifo status change etc from the actual data collector in the bound module). 

 

 

Erling