desperado Posted November 25, 2010 Report Share Posted November 25, 2010 Hi All, Doubt is connect a VHDL DUT With an SV Interface!!! This is first declaration of a signal in vhdl like below:: type t_ar7_0 is array (natural range<>) of std_logic_vector(7 downto 0); This they have used to create a packed dimensional in vhdl for a port signal in the top module as given below:: ABC_MMM : out t_ar7_0(1 to 8); So its like 7 to 0 of 1 to 8 signal in vhdl... Now I had declared a counter part in interface to connect this module as logic [1:8] [7:0] abc_mmm; Now, in a module how to connect these two signals,, I tried like this but its giving illegal port connect for VHDL type. // DUT instance ABC abc_dut (.ABC_MMM(interface.abc_mmm)); How can i Connect a sort of array port declaration in VHDL with SV interface!!! Quite urgent help out plz.. Thanks, Desperado Quote Link to comment Share on other sites More sharing options...
stephenh Posted November 25, 2010 Report Share Posted November 25, 2010 I'm not sure if you're allowed to connect a 2D port across the vhdl-verilog boundary. Remember that there is no official standard for vhdl-verilog integration, so different vendors may support different things. Have you tried creating 8 intermediate wires of [7:0] and assigning them to the slices of the vhdl port? Start with something simple, and build up to what you want... Quote Link to comment Share on other sites More sharing options...
mrmikehicks Posted July 19, 2011 Report Share Posted July 19, 2011 I would also like help connecting a VHDL DUT to a SV virtual interface or help with the bind concept. I have seen several articles on connecting VHDL DUT to SVA but not as virtual interface to connect to the testbench. I am looking for an example of a simple VHDL DUT virtual interface to a UVM based testbench. The VHDL DUT has std_logic, and std_logic_vector ports, nothing fancy. None of the examples seem to address the simple connection of VHDL DUT to the SV bench. Thank You. Quote Link to comment Share on other sites More sharing options...
uwes Posted July 20, 2011 Report Share Posted July 20, 2011 hi, there are a couple of things to consider here. first: an "virtual interface" is just a reference to a real interface instance in sv. with that you simply ask "how can i connect an system verilog interface to a vhdl DUT" - well that is not a UVM problem. and that is a simple question of what your simulator supports. - you can probably instantiate your vhdl dut in the verilog tb. then you can access the ports of your verilog instance as if they were verilog. this looks like: library ieee; use ieee.std_logic_1164.all; entity test105 is port ( clk: in std_ulogic ); end test105; architecture rtl of test105 is begin end rtl; interface test105if; bit clock=0; endinterface module tb; test105if mif(); test105 my(mif.clock); endmodule - depending on your simulator you may also access signals inside the vhdl via OOMR or via other backdoor mechanisms ($nc_mirror and similar) - using bind (depends upon your simulator) interface test105if; bit clock=0; endinterface interface test105rstif(input rst); endinterface module tb; test105if mif(); test105 myvhdl(mif.clock); endmodule bind test105 test105rstif myrstifinst(rst); library ieee; use ieee.std_logic_1164.all; entity test105 is port ( clk: in std_ulogic ); end test105; architecture rtl of test105 is signal rst : std_ulogic; begin end rtl; Quote Link to comment Share on other sites More sharing options...
mrmikehicks Posted July 20, 2011 Report Share Posted July 20, 2011 Thanks Uwe, that gets me a lot further down the road. Mike Quote Link to comment Share on other sites More sharing options...
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