nndad Posted November 22, 2010 Report Posted November 22, 2010 Hi, Is there a way in UVM where I can use a sequencer without an interface & one that need not be hooked up to any driver. I have a sequence which doing RAL programing and for this purpose I don't need a driver to run it. Currently I've tried creating a sort of a virtual sequencer wherein I just use the macro `uvm_update_sequence_lib. But this one does not execute the way I would expect it. I see that the sequence starts executing the moment I do a create on the sequencer. All the RAL programing is done inside the body function of the sequence. So to get around with it I just create a dummy driver for this intended virtual sequencer and I do the RAL programing there. Ideally I want this to be done at a higher level like directly in the sequence without the need for a driver. Any suggestions on how do I go about this? Thanks, -Nishit Quote
uwes Posted November 25, 2010 Report Posted November 25, 2010 hi, sequencers are controlled by their downstream drivers. so you have to have a "whatever driver" which is pulling sequence items from the sequence. you can use something like the attached standalone sequencer // test: irun -uvmhome ~/src/uvm/distrib ies-tests/test42.sv ~/src/uvm/distrib/src/dpi/uvm_dpi.cc module test42; import uvm_pkg::*; `include "uvm_macros.svh" class a_tr extends uvm_sequence_item; `uvm_object_utils(a_tr) function new(string name = "a_tr"); super.new(name); endfunction : new endclass class uvm_nodriver_sequencer#(type A=uvm_sequence_item,type B=A) extends uvm_push_sequencer#(A,; class dummy_push_driver extends uvm_push_driver#(A,; `uvm_component_utils(dummy_push_driver) function new (string name = "dummy_push_driver", uvm_component parent = null); super.new(name, parent); endfunction : new virtual task put(A item); endtask endclass local dummy_push_driver _driver= new("dummy_push_driver",this); `uvm_sequencer_param_utils(uvm_nodriver_sequencer#(A,) virtual function void connect(); super.connect(); req_port.connect(_driver.req_export); endfunction function new (string name = "uvm_nodriver_sequencer", uvm_component parent = null); super.new(name, parent); `uvm_update_sequence_lib_and_item(A) endfunction : new virtual function void build(); super.build(); _driver.build(); endfunction function void start_of_simulation(); print(); endfunction endclass class a_seq extends uvm_sequence#(a_tr); `uvm_sequence_utils(a_seq, uvm_nodriver_sequencer#(a_tr)) function new(string name = "a_seq"); super.new(name); endfunction : new virtual task body(); `uvm_info("test42","here we go",UVM_NONE) `uvm_do(req) `uvm_info("test42","here we go",UVM_NONE) endtask endclass uvm_nodriver_sequencer#(a_tr) my_sqr = new("sequencer",null); initial begin set_config_string("*", "default_sequence", "a_seq"); run_test(); end endmodule Quote
wkongzhu Posted January 6, 2011 Report Posted January 6, 2011 Thanks! But I use questasim6.4C, it does not support neted class. So, move the class definition out just like below: module test42; import uvm_pkg::*; `include "uvm_macros.svh" class a_tr extends uvm_sequence_item; `uvm_object_utils(a_tr) function new(string name = "a_tr"); super.new(name); endfunction : new endclass class dummy_push_driver#(type A=uvm_sequence_item, type B=A) extends uvm_push_driver#(A, ; `uvm_component_utils(dummy_push_driver) function new (string name = "dummy_push_driver", uvm_component parent = null); super.new(name, parent); endfunction : new virtual task put(A item); endtask endclass class uvm_nodriver_sequencer#(type A=uvm_sequence_item,type B=A) extends uvm_push_sequencer#(A,; local dummy_push_driver#(A, _driver= new("dummy_push_driver",this); `uvm_sequencer_param_utils(uvm_nodriver_sequencer#(A,) virtual function void connect(); super.connect(); req_port.connect(_driver.req_export); endfunction function new (string name = "uvm_nodriver_sequencer", uvm_component parent = null); super.new(name, parent); `uvm_update_sequence_lib_and_item(A) endfunction : new virtual function void build(); super.build(); _driver.build(); endfunction function void start_of_simulation(); print(); endfunction endclass class a_seq extends uvm_sequence#(a_tr); `uvm_sequence_utils(a_seq, uvm_nodriver_sequencer#(a_tr)) function new(string name = "a_seq"); super.new(name); endfunction : new virtual task body(); `uvm_info("test42","here we go",UVM_NONE) `uvm_do(req) `uvm_info("test42","here we go",UVM_NONE) endtask endclass uvm_nodriver_sequencer#(a_tr) my_sqr = new("sequencer",null); initial begin set_config_string("*", "default_sequence", "a_seq"); run_test(); end endmodule // test42 Quote
nndad Posted January 6, 2011 Author Report Posted January 6, 2011 Hi, Thanks to everyone for helping me out here. I actually figured out what was the real problem in my case. Whenever I was trying to run the register programing sequence which does not send out any transaction item to sequencer, my driver was still finding a transaction from the sequencer. Apparently the sequencer if not configured correctly by default keeps generating random transaction items. So all I had to do is to set the "count" for the sequencer to 0 via the set_config_int(). And so now when I run this sort of virtual sequence the sequencer does not generate any transaction item & I'm able to execute the RAL programing correctly. Thanks, -Nishit Quote
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