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Steraming width in TLM2

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Imagine you have a device such as a UART (serial port) with a transmit data register. Every time you write a byte to this register, it sends the data.


Now imagine you want to send 64 bytes through that stream with a single transaction. So you stream a payload with 64 bytes to the register address (SEND_ADDR) with a streaming width of 1. All 64 bytes are written to the single address.


If the streaming width were set to 64, then the bytes would go to SEND_ADDR+0, SEND_ADDR+1, SEND_ADDR+2, ... , SEND_ADDR+63. In other words, one address per data item.

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