where am i check in code which error : port not bound?

[carter 1]

Hi.

 

If port not bound code error happened, where am i check in this code which error : port not bound?

so confused.

[kartikkg 3]

Hi, Are you using a test bench for that module? If yes check in the test-bench files where the ports are bound. Its possible that one or more of them are not bound to anything.

[carter 1]

Hi, Are you using a test bench for that module? If yes check in the test-bench files where the ports are bound. Its possible that one or more of them are not bound to anything.

hi 

can i make test bench code in sc_main() ? or i have to separate sc_main  and test bench code?

As i think, the test bench code is like this .

sc_main () {

...

adder u_adder("adder")

u_adder.p_in(4);

...

 

sc_start()

sc_stop()

,,,

}

 

Error : complete binding failed : port not bound: port `adder.port_1' (sc_in)

[kartikkg 3]

yes that seems to be fine, I assume that you have  written an module of adder which will be in some  adder.h file , In a new test_adder.cpp file you can do something like this

#include"adder.h"

int sc_main() int argc, char* argv[]) {

 

sc_in<bool> a_in;

sc_in<bool> b_in;

sc_in<bool> carry_in;

sc_out<bool> sum_out;

......

 

adder u_adder("adder");

u_adder.p_in(a_in);

u_adder.q_in(b_in);

...

 

sc_start()

sc_stop()

[carter 1]

yes that seems to be fine, I assume that you have  written an module of adder which will be in some  adder.h file , In a new test_adder.cpp file you can do something like this

#include"adder.h"

int sc_main() int argc, char* argv[]) {

 

sc_in<bool> a_in;

sc_in<bool> b_in;

sc_in<bool> carry_in;

sc_out<bool> sum_out;

......

 

adder u_adder("adder");

u_adder.p_in(a_in);

u_adder.q_in(b_in);

...

 

sc_start()

sc_stop()

should i make separate like adder header file?

[kartikkg 3]

No need for separate header file.

[carter 1]

No need for separate header file.

Thanks but i'm not sure your answer.

Is this right about should i use another module for test?

[kartikkg 3]

I had same doubts as you , please see this question hope it clears the doubt

http://stackoverflow.com/questions/17269378/systemc-sensitivity-list-behaviour-driving-the-pins-from-main-program

[carter 1]

I had same doubts as you , please see this question hope it clears the doubt

http://stackoverflow.com/questions/17269378/systemc-sensitivity-list-behaviour-driving-the-pins-from-main-program

Thanks

When i change like this "digital_and1 (a_in , b_in , c_out);", anyway i can test passed.

adder u_adder("adder");

u_adder(clk1, data ,   addr );

 

 

 

but  i still have question , why i'm not have passed like following coded ?(port not bound..., no match for cal..bla~bla~)

 

adder u_adder("adder");

u_adder.p_in(clk1);

u_adder.q_in(data);

...

?

[kartikkg 3]

but  i still have question , why i'm not have passed like following coded ?(port not bound..., no match for cal..bla~bla~)

 

adder u_adder("adder");

u_adder.p_in(clk1);

u_adder.q_in(data);

...

?

You must have missed some ports.

[carter 1]

You must have missed some ports.

Thank you

but it's already solved.