gurunath.kadam Posted October 24, 2012 Report Share Posted October 24, 2012 Hi all, I am creating some sc_signal<vector<T> > ports with a user defined T. I have already found a proper link for the same (answer provided by AR/Ravi, inheriting from STL vector). http://www.accellera...g=msg00004.html But now my question is, I am defining other ports where T will be sc_bv, double etc. So shall I write above code for each of the variable type or is it ok with all? (I am particularly worried about << and ==). Thank you. P.S. Will next IEEE1666 talk about sc_vector? Will some provision for above scenario provided in later versions? Quote Link to comment Share on other sites More sharing options...
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