jsmith125x Posted January 22, 2014 Report Share Posted January 22, 2014 Hi, How to convert sc_bool to sc_logic? I have a clock which is connected to an and gate. The gate accepts sc_logic signals. Quote Link to comment Share on other sites More sharing options...
dakupoto Posted January 23, 2014 Report Share Posted January 23, 2014 Hi, How to convert sc_bool to sc_logic? I have a clock which is connected to an and gate. The gate accepts sc_logic signals. Hello Sir, First of all, are you sure there is any data type "sc_bool" ? If so, what is the difference between the built-in C++ datatype "bool" and "sc_bool" ? Using the standard C++ bool datatype the conversion from bool to sc_bool is simple, using string literals. Let us suppose there is a Boolean variable 'bb' and a sc_logic variable sc_l as: bool bb; sc_dt::sc_logic sc_l; /* some processing * here .. */ sc_l = bb == true ? '1' : '0'; /* Reverse conversion */ bb = sc_l == '1' ? true : false; Note that sc_logic can take on two other values: 'X' : dont't care state 'Z' : high impedance state Hope that helps. karandeep963 1 Quote Link to comment Share on other sites More sharing options...
jsmith125x Posted January 23, 2014 Author Report Share Posted January 23, 2014 My problem, I cannot connect a clock to my and gate module. I have got compiler errors. int sc_main(int argc, char* argv[]) { sc_signal<sc_logic> q,c,b,a; sc_signal<sc_logic> N2_1,N0; sc_clock clk("clk", 1, SC_US, 0.5, 0, SC_US, true); org U1("U1"); U1.I1(clk); U1.I2(c); U1.Q(q); andg U2("U2"); U2.I1(a); U2.I2(; U2.Q(N2_1); testbench TB("TB"); TB << q << c << b << a; monitor MON("MON"); MON << q << c << b << a; sc_start(10, SC_US); return 0; } ... #ifndef andgH #define andgH #include "systemc.h" SC_MODULE(andg) { sc_in<sc_logic> I1, I2; // input pins sc_out<sc_logic> Q; // output pin o void proc() { Q = I1 & I2; } SC_CTOR(andg) { SC_METHOD(proc); sensitive << I1 << I2; } }; #endif Or If not works how could I make a clock like in vhdl. process begin clk <= '0'; wait for 1 us; clk <= '1'; wait for 1 us; end process; Quote Link to comment Share on other sites More sharing options...
Hans64 Posted January 23, 2014 Report Share Posted January 23, 2014 I don't believe there is any elegant solution other than changing your U1.I1 input port to type bool or write a separate clock module. In addition to dakupoto answers you can also: sc_l = static_cast<sc_logic> (bb);bb = sc_l.to_bool(); Resolution between 'X'/'Z' and '0'/'1' will not be the same as in VHDL. Good luck,Hans.http://www.ht-lab.com Quote Link to comment Share on other sites More sharing options...
saraswathi.m Posted January 23, 2014 Report Share Posted January 23, 2014 Create a thread process . initialize clk to '0' or '1' clock() { while(1) { clk.write(!clk.read()); wait(1, SC_US); } } Quote Link to comment Share on other sites More sharing options...
dakupoto Posted January 24, 2014 Report Share Posted January 24, 2014 My problem, I cannot connect a clock to my and gate module. I have got compiler errors. int sc_main(int argc, char* argv[]) { sc_signal<sc_logic> q,c,b,a; sc_signal<sc_logic> N2_1,N0; sc_clock clk("clk", 1, SC_US, 0.5, 0, SC_US, true); org U1("U1"); U1.I1(clk); U1.I2(c); U1.Q(q); andg U2("U2"); U2.I1(a); U2.I2(; U2.Q(N2_1); testbench TB("TB"); TB << q << c << b << a; monitor MON("MON"); MON << q << c << b << a; sc_start(10, SC_US); return 0; } ... #ifndef andgH #define andgH #include "systemc.h" SC_MODULE(andg) { sc_in<sc_logic> I1, I2; // input pins sc_out<sc_logic> Q; // output pin o void proc() { Q = I1 & I2; } SC_CTOR(andg) { SC_METHOD(proc); sensitive << I1 << I2; } }; #endif Or If not works how could I make a clock like in vhdl. process begin clk <= '0'; wait for 1 us; clk <= '1'; wait for 1 us; end process; Hello Sir, It appears that there are some fundamental issues that need attention. 1. The AND gate module looks fine -- what exactly is the error message ? 2. HDLs as Verilog/VHDL were designed keeping in mind the special requirements of simulating hardware -- concurrency, clocks, etc., SystemC is a C++ library, and C++ was NOT designed to address the special requirements of hardware design, so one cannot hope to achieve identical end result with SystemC that one does with Verilog/VHDL. A lot of times, workarounds are required. Hope that helps. karandeep963 1 Quote Link to comment Share on other sites More sharing options...
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