Naresh Raghava R Posted January 10, 2014 Report Posted January 10, 2014 Hello, How to include VHDL entity in UVM environment tool I'm using is VCS? Quote
hbeck Posted February 2, 2015 Report Posted February 2, 2015 The same way you are doing it without UVM. I'm using a SV wrapper around the VHDL DUT for interface connection. This wrapper will be used in the testbench toplevel. Also the wrapper is perfectly suited to place all cross module references needed by the testbench. vhdlan -work work vhdl_dut.vhd vlogan -v2k -sverilog sv_wrapper_dut.sv vcs -debug_pp -R my_sv_toplevel Quote
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