VHDL entity in UVM

[Naresh Raghava R]

Hello,

 

How to include VHDL entity in UVM environment tool I'm using is VCS?

[hbeck]

The same way you are doing it without UVM. I'm using a SV wrapper around the VHDL DUT for interface connection. This wrapper will be used in the testbench toplevel. Also the wrapper is perfectly suited to place all cross module references needed by the testbench.

vhdlan -work work vhdl_dut.vhd
vlogan -v2k -sverilog sv_wrapper_dut.sv
vcs -debug_pp -R my_sv_toplevel