Two top moudles in vcs? but sYsTeMcToP always run.

[ethanli]

Hi,

 

I have one SystemC module which is instatiated in my top verilog file.

 

vcs always creates a sYsTeMcToP module for me and simv will just run sc_main() and ignore my own verilog top module.

 

How can I remove sc_main() module and use my own verilog top module instead? Thanks,

[psukhija]

Hi ethanli,

 

          Steps to use VCS, when you want systemc to be instantiated and used are:

 

1)   First compile the systemC files using syscan and on the top module of system C  create a verilog wrapper

      -- example say sc_top is the top system c file

            syscan <   all flags           >  sc_top.cpp:sc_top

       Please note here that sc_top.cpp is wrapped in verilog now with sc_top name, which can be instantiated.

 

2)  use sc_top instance to include in verilog top level, and use -sysc flag on vcs ellaboration to tell that VCS can can expect sysC module inside verilog.

 

 

Thanks,

Piyush