Jump to content


  • Content Count

  • Joined

  • Last visited

  1. Hi, I have one SystemC module which is instatiated in my top verilog file. vcs always creates a sYsTeMcToP module for me and simv will just run sc_main() and ignore my own verilog top module. How can I remove sc_main() module and use my own verilog top module instead? Thanks,
  2. Hi, I download UVM connect 2.2 kit from this website and try to use it connect SC and SV. When I run the examples under directory "connections", sv2sv_native and sc2sc_native are OK. But for sv2sc, sc2sv, sv2sv_uvmc, compiling doesn't give error information. However, it looks like only SC module is running, but SV module didn't not run. [localhost connections]$ make sv2sc -f Makefile.vcs make -f Makefile.vcs clean comp run EXAMPLE=sv2sc make[1]: Entering directory `/home/fpga/uvmc/uvmc-2.2/examples/connections' rm -rf simv* work csrc ucli.key vc_hdrs.h vcs.log AN* *.log *.vpd DVE*
  • Create New...