zareie.ehsan Posted October 27, 2013 Report Share Posted October 27, 2013 Hi is object oriented systemc code synthesizable? for example I defined a new data type (a class) and used it in my code. I don't know I can synthesize it or no. is there any free synthesis tool for systemc? or should I translate my code to Verilog and then synthesize it by existing synthesis tools? Bicspoili 1 Quote Link to comment Share on other sites More sharing options...
Mathieu Posted October 28, 2013 Report Share Posted October 28, 2013 Hi, My experience is that you can synthesize your code if your data type can be converted to a vector (sc_lv) : that is to say data class members are concatenated to a vector. You need to make 2 conversions functions (type_to_vector and vector_to_type) to do this. I don't know any free tool for systemc synthesis (I use catapultc from calypto which is very powerfull but expensive). If you use xilinx, it seems vivado now includes high level synthesis for C/C++/SystemC. Regards,Mathieu Quote Link to comment Share on other sites More sharing options...
zareie.ehsan Posted October 28, 2013 Author Report Share Posted October 28, 2013 thank you Mathieu... my class is : class digit { public: sc_int<4> dt; digit (sc_uint<4> d=0) { dt=d; } digit& operator =(const digit& d) { dt=d.dt; return(*this); } bool operator==(const digit& d) { return(dt==d.dt); } bool isvalid() { return(((dt[3]==1)&& (dt[2]==1)) | ((dt[3]==1)&& (dt[1]==1))); } inline friend ostream& operator<< (ostream& os,const digit& arg) { os<<arg.dt.to_string(SC_DEC)<<endl; return os; } inline friend void sc_trace(sc_trace_file* tf, const digit& arg , const sc_string& NAME) { sc_trace (tf,arg.dt,NAME +".dt"); } }; you mean that I have to use my class as a vector and the concept of my class will change or it have just a simple seeming change? Quote Link to comment Share on other sites More sharing options...
Mathieu Posted October 28, 2013 Report Share Posted October 28, 2013 Ok sorry I wasn't clear : - you can use your class as you want, you don't have to change anything - but if you want to write your digit object to a channel (ex : sc_fifo), it seems to me that you must be able to convert your class to a vector For example (with 2 data members) : class digit { public: sc_int<4> dt1; sc_int<4> dt2; //... }; inline void type_to_vector(const digit & in, int length, sc_lv<8> & rvec) { rvec.range(7,4) = in.dt1; rvec.range(3,0) = in.dt2; } inline void vector_to_type(const sc_lv<8> & in, bool issigned, digit * result) { sc_biguint<8> tmp = in; result->dt1 = tmp.range(7,4); result->dt2 = tmp.range(3,0); } This code is synthesizable. Maybe this is not exactly your question, I just pointed this because you don't have this kind of constraint in C++. Mathieu Quote Link to comment Share on other sites More sharing options...
zareie.ehsan Posted October 28, 2013 Author Report Share Posted October 28, 2013 yes I got it! thank you very much for your helpful reply Quote Link to comment Share on other sites More sharing options...
amitk3553 Posted November 20, 2013 Report Share Posted November 20, 2013 Hi, My experience is that you can synthesize your code if your data type can be converted to a vector (sc_lv) : that is to say data class members are concatenated to a vector. You need to make 2 conversions functions (type_to_vector and vector_to_type) to do this. I don't know any free tool for systemc synthesis (I use catapultc from calypto which is very powerfull but expensive). If you use xilinx, it seems vivado now includes high level synthesis for C/C++/SystemC. Regards, Mathieu catapultc converts systemC/C/C++ code into RTL then do synthesis with another tool or same tool is used to produce netlist from systemC code?? Quote Link to comment Share on other sites More sharing options...
foster911 Posted November 21, 2013 Report Share Posted November 21, 2013 All CatapultC's related FAQs here: http://communities.mentor.com/mgcx/community/asic_fpga/esl Quote Link to comment Share on other sites More sharing options...
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