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  1. All CatapultC's related FAQs here: http://communities.mentor.com/mgcx/community/asic_fpga/esl
  2. This is also another methodology. Simply register and download the source codes. Teal & Truss: http://www.trusster.com/products/teal/ http://www.trusster.com/products/truss/ There is a book named "Hardware Verification with C++" describing the above libraries. I have not put them in practice yet. If someone has any knowledge about them, could light me up please. Do they yield more facilities than SCV. How about AVM?
  3. This is AVM (Advanced Verification Methodology) from Mentor Graphics. This is the only MMM... for SystemC. Could someone please tell that this library is still supported by mentor or not? AVM_3-2 (Cook Book is also included): http://depositfiles.com/files/0k2qh7eni
  4. Dynamic Assertion-Based Verification for SystemC by Deian Tabakov http://www.cs.rice.edu/CS/Verification/Theses/Archive/dtabakov_dissertation2010.pdf Question: Is it possible to do Assertion-Based Verification with pure SystemC and available SCV in reality like the SystemVerilog Assertion does or it needs changing the Kernel or extending the SCV API? How about UVM in SystemC? This could have the advantage of getting rid of language changing.
  5. Some tools do this job for you automatically (like Mentor Vista). In fact your question needs comprehensive answer. I mean you're actually asking the philosophy of emerging and existence of TLM. Short answers to this question just would confound you. You may never find the answer of this question completely just by reading papers (even from IEEE) or looking at the samples due to the complexity of the matter. I suggest you to find a "ground up" book for this question like the one that pre-exists for the SystemC named " SystemC from the Ground Up". I suggest the book mentioned previously
  6. @amitk3553 I have problem sending pm to you. Please give me an email. This book talks about OSCI TLM and OCP TL(recently acquired by Accellera): Accellera Acquires OCP 3.0 Standard http://forums.accellera.org/topic/1518-accellera-acquires-ocp-30-standard/ There is also a book named "Introduction to Open Core Protocol (OCP)" that would be useful too.
  7. Please read: http://forums.accellera.org/topic/1389-use-cases-of-tlm-over-systemc/#entry5784 Please look at the TOC of the book. The whole book answers all of these kinds of questions completely and opens new doors to the TLM 2.0 paradigm. The chapters are not independent and follow previous ones that at the end you could have an allegation of having moderate knowledge about TLM 2.0.
  8. @ mitk3553 As every SystemC user know, modeling in TLM2 is the most complicated job for the developers and because of misunderstanding the TLM concept, it seems that TLM2 would be undiscoverable. I believe that most aspects of modeling and verification tasks are for software designers not hardware ones. TLM2 is one of those aspects and the reason why hardware designers with verilog background have always trouble with that is this. STARC Transaction-Level Modeling (TLM) Guide is the best reference for TLM2 in the web and will answer all of your questions. This is only first 50 page
  9. extensions to C++ for lightweight multithreading in a way similar to that found in HDLs (e.g. Verilog and VHDL). The extended language should be a replacement for most HDLs and SystemC as well as being usable for programming many-core and distributed parallel systems. ParC is being developed as part of the V2000 open-source simulator project. ......................... Motivation Problems with existing MT/parallel approaches Having worked on a few SMP parallel processing projects using pThreads and Quickthreads with C/C++, it became obvious fairly quickly that there are a number of problems wit
  10. The complexity of modern embedded systems, which are increasingly based on heterogeneous MultiProcessor-SoC (MP-SoC) architectures, has led to the emergence of system-level design. To cope with this design complexity, system-level design aims at raising the abstraction level of the design process. Key enablers to this end are, for example, the use of architectural platforms to facilitate re-use of IP components and the notion of high-level system modeling and simulation. The latter allows for capturing the behavior of platform components and their interactions at a high level of abstraction. A
  11. As everyone know, being able to view VCD files inside the verification platforms like Mentor QuestaSim (or ModelSim) or Aldec Riviera needs below commands respectively: vcd2wlf vcd2asdb Then by simply dragging the generated *.wlf and *.asdb files inside the tools, traced objects can be viewed in the waveform window. I did the above procedures for your VCD file and was able to view them without any error inside both tools. I suggest you also do that instead of trying to use gtkwave.
  12. Sorry for duplication! Any way to remove this? Thanks!
  13. ArchC is a powerful and modern open-source architecture description language designed at University of Campinas by the ArchC team in the Computer Systems Laboratory, Institute of Computing. Our goal in designing ArchC is to provide architecture designers with a tool that allows them to rapidly evaluate new ideas in areas such as: processor and ISA design, memory hierarchy, and other aspects of computer architecture research. Fast prototyping Easy to use language, describes hardware and processor using high level hardware abstractions. ISA simulator ArchC generates compiled and interpreted
  14. There are 2 tedious tasks in the field of ESL and SOC: 1- Microprocessor model creation and Compiler and Driver development 2- Hardware/Software partitioning and interfacing them together. For the second part, please read below DOC. It's not related to SystemC but can reveal lots of ambiguities. Hardware(Verilog or VHDL)/Software(C or assembly)/Micro-processor tuning and mixing http://depositfiles.com/files/grlag48ee
  15. Most synthesis tools recommend fixed size arrays.
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