Interface Monitor implementation

[paragsathe]

Hi,

 

I have a interface monitor where i am capturing data from the interface.

I need to pass valid data captured from the interface to the scoreboard for comparison.

 

But the behaviour of interface signals and the way they are asserted depends on the register configuration.

Now this config info is not known to the interface or the interface monitor.

So while implementing the monitor, should i define two monitors

1) interface monitor which just samples all the data from the bus.

2) process data got in 1) furthur depending on the register config & then pass it on the scoreboard for comparison.

 

 

Also should this be done using analysis ports?

I think this is the right way but wanted to know if there is anything that UVM recommends in such cases.

 

Thanks in advance.

Parag