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Showing results for tags 'monitor'.
Hi, I started to play around with the basic scoreboard example provided in the uvm-systemC 1.0 beta 2 release. I was trying to enhance the example by adding a clock and a reset signal in the sc_main. Then I wanted to modify the vip_if to add a reset and clock signal. My goal was to implement a driver/monitor run phase that drives/samples the sig_data signal on the rising edge of the clock. I am struggling to do so... Is there such an example that exists or that someone could share ?
I am learning UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env. Sequences to send valid data to DUT. I yet to implement scoreboard. I'm having some trouble to understand how to handle scenarios like following: For one of my tb->dut interfaces, TB needs to wait for an event (or transaction) from DUT. Once it receives the transaction from DUT, TB needs to send back a response. What is the best way to implement this? How can I monitor DUT transacti
Hi, I have a interface monitor where i am capturing data from the interface. I need to pass valid data captured from the interface to the scoreboard for comparison. But the behaviour of interface signals and the way they are asserted depends on the register configuration. Now this config info is not known to the interface or the interface monitor. So while implementing the monitor, should i define two monitors 1) interface monitor which just samples all the data from the bus. 2) process data got in 1) furthur depending on the register config & then pass it on the scoreboard fo