foster911 Posted October 19, 2013 Report Share Posted October 19, 2013 Dynamic Assertion-Based Verification for SystemC by Deian Tabakov http://www.cs.rice.edu/CS/Verification/Theses/Archive/dtabakov_dissertation2010.pdf Question: Is it possible to do Assertion-Based Verification with pure SystemC and available SCV in reality like the SystemVerilog Assertion does or it needs changing the Kernel or extending the SCV API? How about UVM in SystemC? This could have the advantage of getting rid of language changing. Quote Link to comment Share on other sites More sharing options...
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