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problem with the timings of the outputs


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Hi all,

  I am new to systemC and i am trying to create two modules( a constant and counter module) and trying to make a connection between them and see the outputs and see how the data flows.


please see the code of the modules and connection between them.



#include "systemc.h"
#include <stdlib.h>
#include <iostream>

sc_in<bool> clk;
sc_out<bool> output;
bool A;
void process(){    
cout<< "@"<< sc_time_stamp() << " ::constant output written" << output << endl;
sensitive << clk.pos();




#include <systemc.h>
#include <iostream>

SC_MODULE (counter) {
  sc_in<bool> reset;
  sc_in<bool> enable;
  sc_out< sc_ufixed< 12,12, SC_TRN, SC_SAT> > counter_out;

  sc_ufixed < 12,12, SC_TRN, SC_SAT> count;

   void incr_count () {
   if (reset.read() == 1) {
      count =  0;
      cout<<"@" << sc_time_stamp()<< "::COUNTER IS RESET " <<  counter_out.read() << endl;
     if (enable.read() == 1) {
      cout<<"@" << sc_time_stamp() <<" :: Incremented Counter "<<counter_out.read()<<endl;
    SC_CTOR(counter) {
     cout<< " executing counter"<< endl;
        sensitive  <<reset << enable ;



#include "systemc.h"
#include "counter.h"
#include "constant.h"
int sc_main (int argc, char* argv[]) {

    sc_buffer<bool> rstsignal;
    sc_buffer<bool> ensignal;
    sc_buffer <sc_ufixed<12,12, SC_TRN, SC_SAT > >outputsignal;
    sc_clock clock("CLOCK", 1, SC_SEC);

    constant c1("constant");

    counter c2("counter");

      rstsignal = 0;
      sc_start(3, SC_SEC);
      rstsignal = 1;
      sc_start(3, SC_SEC);
return 0;





 executing counter

@0 s :: constant output written 0
@0 s :: Incremented Counter     0
@0 s :: constant output written 1
@0 s :: Incremented Counter     1
@1 s :: constant output written 1
@1 s :: Incremented Counter     2
@2 s :: constant output written 1
@2 s :: Incremented Counter     3
@3 s::  COUNTER IS RESET        4
@3 s :: Incremented Counter     4
@3 s ::constant output written  1
@3 s:: COUNTER IS RESET         1
@3 s :: Incremented Counter     1
@4 s :: constant output written 1
@4 s:: COUNTER IS RESET         1
@4 s :: Incremented Counter     1
@5 s ::constant output written  1
@5 s:: COUNTER IS RESET         1
@5 s :: Incremented Counter     1


As expected whenever there is posedge clock , the constant module produces the output and the counter module is getting incremented.


But as you can see @0s and @3s i am getting two outputs of the counter module. 


 Can anyone what is the reason behind it ? which output  should i consider ? and do i need to change any timing constraints to avoid it?


Thanks in advance.

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At time 0, all processes execute independent of their static sensitivity list, unless you use dont_initialize(). That's why you see two executions at time 0, your constant process runs once at time zero, then runs a delta later when the rising edge of the clock occurs. If you want to remove this, change the process declaration to


sensitive << clk.pos();


Regarding time 3s, I expect the reset signal is changing on a different delta than the enable signal, and thus triggering the process twice.


You can test this by printing out the delta count as well as the time - you can use the function sc_delta_count() to return the current delta count.


For a tutorial which includes a discussion of dont_initialize(), have a look at



kind regards


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Dear Alan,


Thanks for the response. i have read about dont_initialize() on your website, it gave a nice explanation and understood that it is used to avoid  initializing the process without the sensitivity list event occurrence.


But at @3s the reset signal has the transition from 0 to 1. so as you mentioned it works on the different delta cycles and so it is getting triggering twice.


i tried to print out the delta counts @3s


@3 s ::  COUNTER IS RESET =3,      delta cycle=13
@3 s :: Incremented Counter =3,    delta cycle=13
@3 s :: constant output written=1, delta cycle=13
@3 s ::  COUNTER IS RESET=1,       delta cycle=14
@3 s :: Incremented Counter=1,     delta cycle=14


so is there any method to avoid these double triggering wrt to the delta cycles?

Because when try i simulate for large number of seconds I will get the big difference in incremented counter values wrt to number of secs.


Thanks in advance.

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Essentially this is the point of synchronous design. If you can, trigger everything in your code from a single clock source, then you don't need the reset and enable in the sensitivity list. As long as you make sure the signals you sample are stable at the point when the clock changes from 0 to 1, everything will work in a predictable fashion,


kind regards


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