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Rahul

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  1. hi all, I am just starting my practical implementations in systemC. Below i have implemented a constant module which produces the constant o/p and it is connected to a counter module. constant.h #define SC_INCLUDE_FX #include "systemc.h" #include <stdlib.h> SC_MODULE(constant){ sc_out<bool> output; int A; void process(){ // while(true) { wait(19,SC_MS); // sample time + delay A=1; output.write(A); cout<< "@"<<sc_time_stamp() << " ::constant output written" << output << endl; } } SC_CTOR(constant) { SC_THREAD(process); } }; counter.h #include <systemc.h> #include <iostream> #define SC_INCLUDE_FX SC_MODULE (counter) { sc_in<bool> reset; sc_in<bool> enable; sc_out<sc_ufixed<12,12, SC_TRN, SC_SAT> > counter_out; sc_ufixed<12,12, SC_TRN, SC_SAT> count; void incr_count () { while(true){ wait(19, SC_MS); if (reset.read() == 1) { count = 0; counter_out.write(count); cout<<"@" << sc_time_stamp()<< "::COUNTER IS RESET " << counter_out.read() << endl; } if (enable.read() == 1) { count=count+1; counter_out.write(count); cout<<"@" << sc_time_stamp() <<" :: Incremented Counter "<<counter_out.read()<<endl; } } } SC_CTOR(counter) { cout<< " executing counter"<< endl; SC_THREAD(incr_count); dont_initialize(); sensitive <<reset << enable ; } }; test.cpp #define SC_INCLUDE_FX #include "count.h" #include "constant.h" #include "systemc.h" int sc_main (int argc, char* argv[]) { sc_buffer<sc_ufixed<8,8, SC_TRN, SC_SAT> > dinsignal; sc_buffer<bool> rstsignal; sc_buffer<bool> ensignal; sc_buffer <sc_ufixed<12,12, SC_TRN, SC_SAT > >outputsignal; constant c1("constant"); c1.output(ensignal); counter c2("counter"); c2.reset(rstsignal); c2.enable(ensignal); c2.counter_out(outputsignal); sc_trace_file *tf = sc_create_vcd_trace_file("VCD test"); // External Signals sc_trace(tf, ensignal, "Enable signal"); sc_trace(tf, outputsignal, "output signal"); rstsignal = 1; sc_start(1, SC_SEC); rstsignal = 0; sc_start(1, SC_SEC); sc_close_vcd_trace_file(tf); return 0; } The module's works correctly as i expected. But the problem is with the vcd trace file. The main module produces a vcd file of type .vcd format but when i tried to open it in the gtkwave viewer, the vcd file cannot be opened. There is no error message also for debugging the problem. So I thought of debugging the vcd file in a text editor and found this output date Oct 08, 2013 15:38:51 $end $version SystemC 2.3.0-ASI --- Aug 26 2013 11:03:53 $end $timescale 1 ps $end $scope module SystemC $end $var wire 1 aaa Enable signal $end $var wire 12 aab output signal [11:0] $end $upscope $end $enddefinitions $end $comment All initial values are dumped below at time 0 sec = 0 timescale units. $end $dumpvars 0aaa b0 aab $end #19000000000 1aaa #38000000000 b1 aab .... .... .... As you can see the comment in the tracefile So is this the reason the vcd file cannot be opened? if yes, what changes do i need to do in the main module to get worked? (or) the problem would be related to installation of gtkwave viewer? Please help me how to proceed to the problem solution. Thanks in advance.
  2. Dear Alan, Thanks for the response. i have read about dont_initialize() on your website, it gave a nice explanation and understood that it is used to avoid initializing the process without the sensitivity list event occurrence. But at @3s the reset signal has the transition from 0 to 1. so as you mentioned it works on the different delta cycles and so it is getting triggering twice. i tried to print out the delta counts @3s outputs @3 s :: COUNTER IS RESET =3, delta cycle=13 @3 s :: Incremented Counter =3, delta cycle=13 @3 s :: constant output written=1, delta cycle=13 @3 s :: COUNTER IS RESET=1, delta cycle=14 @3 s :: Incremented Counter=1, delta cycle=14 so is there any method to avoid these double triggering wrt to the delta cycles? Because when try i simulate for large number of seconds I will get the big difference in incremented counter values wrt to number of secs. Thanks in advance.
  3. Hi all, I am new to systemC and i am trying to create two modules( a constant and counter module) and trying to make a connection between them and see the outputs and see how the data flows. please see the code of the modules and connection between them. Constant.h #include "systemc.h" #include <stdlib.h> #include <iostream> SC_MODULE(constant) { sc_in<bool> clk; sc_out<bool> output; bool A; void process(){ A=1; output.write(A); cout<< "@"<< sc_time_stamp() << " ::constant output written" << output << endl; } SC_CTOR(constant){ SC_METHOD(process); sensitive << clk.pos(); } }; counter.h #define SC_INCLUDE_FX #include <systemc.h> #include <iostream> SC_MODULE (counter) { sc_in<bool> reset; sc_in<bool> enable; sc_out< sc_ufixed< 12,12, SC_TRN, SC_SAT> > counter_out; sc_ufixed < 12,12, SC_TRN, SC_SAT> count; void incr_count () { if (reset.read() == 1) { count = 0; counter_out.write(count); cout<<"@" << sc_time_stamp()<< "::COUNTER IS RESET " << counter_out.read() << endl; } if (enable.read() == 1) { count=count+1; counter_out.write(count); cout<<"@" << sc_time_stamp() <<" :: Incremented Counter "<<counter_out.read()<<endl; } } SC_CTOR(counter) { cout<< " executing counter"<< endl; SC_METHOD(incr_count); sensitive <<reset << enable ; } }; test.cpp #define SC_INCLUDE_FX #include "systemc.h" #include "counter.h" #include "constant.h" int sc_main (int argc, char* argv[]) { sc_buffer<bool> rstsignal; sc_buffer<bool> ensignal; sc_buffer <sc_ufixed<12,12, SC_TRN, SC_SAT > >outputsignal; sc_clock clock("CLOCK", 1, SC_SEC); constant c1("constant"); c1.clk(clock); c1.output(ensignal); counter c2("counter"); c2.reset(rstsignal); c2.enable(ensignal); c2.counter_out(outputsignal); rstsignal = 0; sc_start(3, SC_SEC); rstsignal = 1; sc_start(3, SC_SEC); return 0; } output executing counter @0 s :: constant output written 0 @0 s :: Incremented Counter 0 @0 s :: constant output written 1 @0 s :: Incremented Counter 1 @1 s :: constant output written 1 @1 s :: Incremented Counter 2 @2 s :: constant output written 1 @2 s :: Incremented Counter 3 @3 s:: COUNTER IS RESET 4 @3 s :: Incremented Counter 4 @3 s ::constant output written 1 @3 s:: COUNTER IS RESET 1 @3 s :: Incremented Counter 1 @4 s :: constant output written 1 @4 s:: COUNTER IS RESET 1 @4 s :: Incremented Counter 1 @5 s ::constant output written 1 @5 s:: COUNTER IS RESET 1 @5 s :: Incremented Counter 1 As expected whenever there is posedge clock , the constant module produces the output and the counter module is getting incremented. But as you can see @0s and @3s i am getting two outputs of the counter module. Can anyone what is the reason behind it ? which output should i consider ? and do i need to change any timing constraints to avoid it? Thanks in advance.
  4. Though i am not an expert in a systemC. i can provide some information about sc_fifo and its methods and usage. CHANNELS IN SYSTEM C •A channel implements one or more interfaces, and serves as a container for communication functionality •Different channels may implement the same interface in different ways •A channel may implement more than one interface •A channel may be connected to more than two modules •A distinction is made between primitive channelsand hierarchical channels Primitive channels: sc_fifo is type of Primitive channels used largely in systemC •A channel is primitive when it does not contain any hierarchy or process •All primitive channels are derived from the base class called sc_prim_channel •SystemC contains several built-in channels. The simplest are: sc_signal, sc_mutex, sc_semaphore and sc_fifo sc_fifo By default, an sc_fifo<> has a depth of 16. The data type (i.e.,typename) of the elements also needs to be specified. An sc_fifo may contain any data type including large and complex structures Implements interface: sc_fifo_in_if, sc_fifo_out_if Methods: nb_read() Non-blocking read, returns bool, false if fifo is empty, true if read successful read() Returns current value of signal . Blocking for sc_fifo read(port/signal) Returns void, current value of signal is stored in port_or_signal. Blocking for sc_fifo operator=() Assignment operator For convenience, does a write() write(val) Schedules val to be written to the signal at the next update phase. Blocking for sc_fifo nb_write(val) Non-blocking write, returns bool, false if fifo is full, true if write successful num_free() Returns int, number of remaining elements that can be written before fifo is full num_available() Returns int, number of elements that are in the fifo kind() Returns channel type (sc_buffer or sc_fifo etc) Custom ports: sc_fifo_in<T>, sc_fifo_out<T> Specify fifo depth in sc_main: sc_fifo<T> f(10); //Depth is 10 Specify fifo depth in a module: SC_CTOR(module_name): f(10) Regards Rahul
  5. Dear Mr. Alan Fitch, Thank you for the reply. Yes as you mentioned using sc_buffer would be the right way to connect the modules rather than a sc_signal when there is a same output. i tried following the same way, the sc_buffer gets updated every time the output writes. But the counter is not getting incremented as expected. Its getting reset every alternative positive edge rather than getting incremented with the previous value. Is there again any problem in signal updation or in the design of a counter? please help me how to proceed with it executing counter @0 s ::constant output written 0 @0 s :: Incremented Counter 0 @1 s ::constant output written 1 @1 s :: Incremented Counter 1 @3 s ::constant output written 1 @3 s :: Incremented Counter 0 @5 s ::constant output written 1 @5 s :: Incremented Counter 1 @7 s ::constant output written 1 @7 s :: Incremented Counter 0 @9 s ::constant output written 1 @9 s :: Incremented Counter 1
  6. please note : i have updated my question more clearly above
  7. UPDATED QUESTION hi all, I am very new to systemC and i have finished the theoretical concepts in systemc and just started with the simple implementations. Here i have tried to implemented a constant module, which is source a module providing outputs (1) at each positive clock edge and this module output is connected to the enable input of the next counter module. The clock input to the constant module are provided manually in the cpp file. pls see the following codes and the output. constant module #ifndef CONSTANT_H_ #define CONSTANT_H_ #include "systemc.h" #include <stdlib.h> SC_MODULE(constant){ sc_in<bool> clk; sc_out<bool> output; bool A; void process(){ // A=1; output.write(A); cout<< "@"<<sc_time_stamp() << " ::constant output written" << output << endl; } SC_CTOR(constant) { SC_METHOD(process); sensitive << clk.pos(); } }; #endif /* CONSTANT_H_ */ counter.h #ifndef COUNTER_H_ #define COUNTER_H_ #define SC_INCLUDE_FX #include "systemc.h" #include <iostream> SC_MODULE (counter) { sc_in<bool> enable; sc_out<sc_uint<1> > counter_out; sc_uint<1> count; void incr_count () { if (enable.read() == 1) { count=count+1; counter_out.write(count); cout<<"@" << sc_time_stamp() <<" :: Incremented Counter "<<counter_out.read()<<endl; } } SC_CTOR(counter) { cout<< " executing counter"<< endl; SC_METHOD(incr_count); sensitive << enable ; } }; #endif /* COUNTER_H_ */ test.cpp #include "systemc.h" #include "counter.h" #include "constant.h" int sc_main (int argc, char* argv[]) { sc_signal<bool> clock; sc_signal<bool> ensignal; sc_signal<sc_uint<1> > outputsignal; constant c1("constant"); c1.clk(clock); c1.output(ensignal); counter c2("counter"); c2.enable(ensignal); c2.counter_out(outputsignal); for (int i=0;i<5;i++) { clock = 0; sc_start(1, SC_SEC); clock = 1; sc_start(1, SC_SEC); } sc_stop(); return 0; } output executing counter @0 s ::constant output written0 @0 s :: Incremented Counter 0 @1 s ::constant output written1 @3 s ::constant output written1 @5 s ::constant output written1 @7 s ::constant output written1 @9 s ::constant output written1 As expected, the constant module produces output at each positive clock edge. But the problem is, the output written on the constant output port could not be read on the enable inport of counter module. I guess i have made connections also correct and i couldn't able debug why the counter enable inport cannot read the inputs and not increasing the counter. Any help / pointing out of problem would be a great help to me. Thanks
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