Reading inputs of a counter module

[Rahul]

UPDATED QUESTION

 

hi all,

 

I am very new to systemC and i have finished the theoretical concepts in systemc and just started with the simple implementations.

 

Here i have tried to implemented a constant module, which is source a module providing outputs (1) at each positive clock edge and this module output is connected to the enable input of the next counter module.

 

The clock input to the constant module are provided manually in the cpp file.

 

pls see the following codes and the output.

 

constant module

#ifndef CONSTANT_H_
#define CONSTANT_H_


#include "systemc.h"
#include <stdlib.h>


SC_MODULE(constant){
sc_in<bool> clk;
sc_out<bool> output;


bool A;
void process(){    //
A=1;
output.write(A);
cout<< "@"<<sc_time_stamp() << " ::constant output written" << output << endl;


}


SC_CTOR(constant)
{
SC_METHOD(process);
sensitive << clk.pos();
}
};




#endif /* CONSTANT_H_ */



 

 

 

 

counter.h
#ifndef COUNTER_H_
#define COUNTER_H_


#define SC_INCLUDE_FX
#include "systemc.h"
#include <iostream>


SC_MODULE (counter) {
  sc_in<bool>   enable;
  sc_out<sc_uint<1> > counter_out;


  sc_uint<1> count;


   void incr_count () {
   if (enable.read() == 1) {
  count=count+1;
      counter_out.write(count);
      cout<<"@" << sc_time_stamp() <<" :: Incremented Counter "<<counter_out.read()<<endl;
    }


   }
    SC_CTOR(counter) {
    cout<< " executing counter"<< endl;
    SC_METHOD(incr_count);
        sensitive  << enable ;
    }
};
#endif /* COUNTER_H_ */

 

 

 

 

 

 

 

 

 

 

test.cpp
#include "systemc.h"
#include "counter.h"
#include "constant.h"


int sc_main (int argc, char* argv[]) {
    sc_signal<bool> clock;
    sc_signal<bool> ensignal;
    sc_signal<sc_uint<1> > outputsignal;


    constant c1("constant");
    c1.clk(clock);
    c1.output(ensignal);


    counter c2("counter");
    c2.enable(ensignal);
    c2.counter_out(outputsignal);


    for (int i=0;i<5;i++) {
         clock = 0;
         sc_start(1, SC_SEC);
         clock = 1;
         sc_start(1, SC_SEC);


        }


    sc_stop();
    return 0;
}

 

 

 

 

 

 

output
executing counter
@0 s ::constant output written0
@0 s :: Incremented Counter 0
@1 s ::constant output written1
@3 s ::constant output written1
@5 s ::constant output written1
@7 s ::constant output written1
@9 s ::constant output written1
 

 

 

 

As expected, the constant module produces output at each positive clock edge.

 

But the problem is, the output written on the constant output port could not be read on the enable inport of counter module.

 

I guess i have made connections also correct and i couldn't able debug why the counter enable inport cannot read the inputs and not increasing the counter.

 

Any help / pointing out of problem would be a great help to me.

 

Thanks

 

 

 

[Rahul]

please note : i have updated my question more clearly above 

[apfitch]

The sc_signal class only creates events when it changes value. Because you assign the same value all the time, the counter never gets triggered.

 

Try changing sc_signal<bool> ensignal to sc_buffer<bool> ensignal;

sc_buffer is a derived class of sc_signal that notifies an event when it is written, even if you write the same value over and over again.

 

regards

Alan

 

P.S.

To generate your clock, it would be easier (in sc_main) to do

 

sc_clock clock("clock", 1, SC_SEC);

 

...

 

sc_start(10, SC_SEC);

 

The sc_clock instance can be directly bound to a port of type sc_in<bool>.

[Rahul]

Dear Mr. Alan Fitch, Thank you for the reply.

Yes as you mentioned using sc_buffer would be the right way to connect the modules rather than a sc_signal when there is a same output.

i tried following the same way, the sc_buffer gets updated every time the output writes. But the counter is not getting incremented as expected.

Its getting reset every alternative positive edge rather than getting incremented with the previous value.

 

Is there again any problem in signal updation or in the design of a counter? please help me how to proceed with it

 

 

 

executing counter
@0 s ::constant output written 0
@0 s :: Incremented Counter    0
@1 s ::constant output written 1
@1 s :: Incremented Counter    1
@3 s ::constant output written 1
@3 s :: Incremented Counter    0
@5 s ::constant output written 1
@5 s :: Incremented Counter    1
@7 s ::constant output written 1
@7 s :: Incremented Counter    0
@9 s ::constant output written 1
@9 s :: Incremented Counter    1
 

[apfitch]

You need to give more bits to counter_out, at the moment it is only 1 bit,

 

Alan